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RTOS/PROCESSOR-SDK-AM335X: SYS/BIOS timer (DMTIMER2) issue

Jiri Biel
Intellectual 865 points
Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hello,

I'm using CCS v.8.3.0 with TI RTOS 5.01.00.11 and I have a problem on AM335x ICEv2 board.

The SYS/BIOS is using for clock generating DMTIMER2 as default what I get after some debug time.

This timer should be disabled after reset as mentioned in Technical Reference Manual Rev. P (register CM_PER_TIMER2_CLKCTRL).

Also DMTIMER0 (register CM_WKUP_TIMER0_CLKCTRL) should be disabled, but directly after the start of debug (breakpoint on c_init), just after apply of gel script I see that both are enabled.

I was looking to delivered GEL file (TMDXICE3359.gel), but there is nothing about enabling of these timers.

Means first question is how these timers are enabled?

Another problem is that SYSBIOS was correctly working in debug, but not under Bootloader.

In Bootloader was crashing on check frequency part.

Now my understanding what is happening:

SYSBIOS default timer DMTIMER2 (for AM335x) is using as default 32kHz input frequency.

The CCS is changing register CLKSEL_TIMER2_CLK reset value CLK_M_OSC to CLK_32kHz clock. Here again I want to ask how, because I don't see it in GEL file.


The Bootloader is using default settings of  CLKSEL_TIMER2_CLK means CLK_M_OSC and I can fix crash on frequency check with following configuration:

var DmTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
DmTimer.intFreqs[0] = {hi: 0, lo: 24000000};

But after this, the debug code of course is not working.

Please can you suggest me some solution for this issue, how to fix that it works for both?

With best regards

Jiri

  • 0
    TI__Guru**** 170625 points
    Hi Jiri,

    Please refer to the below e2e threads:

    e2e.ti.com/.../771876
    e2e.ti.com/.../774975

    Let me know if you still have questions regarding DMTIMER usage.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 865 points
    Hi Pavel,
    thank you for a response. My problem is not an activation of the timers, I see that there are active already (I need just DMTIMER2).
    The problem is only that it goes against of Technical Reference Manual which is saying that they needs to be disabled after reset.

    I need to know what is valid, the DMTIMER2 is after reset enabled with input frequency 32kHz?

    If yes, it needs to be fixed in Technical Reference Manual. If not I need to know where it's changed in CCS, becase GEL file is not doing it.

    With best regards
    Jiri
  • 0 in reply to Jiri Biel
    TI__Guru**** 170625 points

    Jiri,

    You refer to DMTIMER2 at addr 0x48040000, correct?

    Regarding RTOS, I found this timer2 might be enable in below file, please check:

    pdk_am335x_x/packages/ti/starterware/soc/am335x/am335x_prcm.c

    enableModule(SOC_CM_PER_REGS, CM_PER_TIMER2_CLKCTRL,
    CM_PER_L4LS_CLKSTCTRL ,
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK);


    Regarding clock source, it might be configured in below files:

    pdk_am335x_x/packages/ti/drv/pm/src/pmhal/prcm/V3/hw_pmhal_data.c
    PMHAL_PRCM_MUX_TIMER2_CLK_MUX_validEnumValues

    pdk_am335x_x/packages/ti/drv/pm/src/pmlib/prcm/V3/pmlib_clk_rate_data_am335x.c

    pdk_am335x_x/packages/ti/starterware/soc/am335x/am335x_control.c
    SOCCtrlTimerClkSrcSelect(uint32_t instance, uint32_t timerClkSrc)

    See also below e2e thread:

    e2e.ti.com/.../1616267

    I will also check in CCS8 GEL files and come back to you.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 865 points
    Hi Pavel,
    thank you for answer. I think, in link which you attached was discussed the same question at the end:

    "The problem is CLKSEL_TIMER2_CLK = 0x02 (CLK_32KHZ) when SysBios starts. The .gel file does not contain any reference to this register, or at least I can't find any reference to that constant or address. TRM spruh73L Sec. 8.1.12.3.2 says CLKSEL is 0x01 (CLK_M_OSC) after reset. Assuming this is correct, something is changing the register value before SysBios starts. Does any SysBios startup code run before BIOS_start() is called?"

    But locked without any answer.

    Yesterday I made some simple test and I saw that DMTIMER2 is enabled directly after reset and input frequency is set to 32kHz.
    Please can you discuss with somebody who is responsible for Technical Reference Manual of AM335x that needs to be fixed there?

    Thank you.
    Jiri
  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points
    Jiri,

    I am not able to find any reference to DMTIMER2 PRCM registers in CCS8 GEL files. So you should focus on the RTOS files I have provided in my previous post.

    Regards,
    Pavel
  • 0 in reply to Jiri Biel
    TI__Guru**** 170625 points
    Jiri,

    Seems that AM335x ROM Code is configuring Timer2, even not documented in TRM, check below e2e thread:

    e2e.ti.com/.../699273

    Regarding TRM update request, you can use the "Submit Documentation Feedback" button located at the bottom of each TRM page.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 865 points
    Hi Pavel,
    thats the point as I wrote before.

    What's the sequence:
    1. Reset
    2. Reset values are loaded to the registers.
    3. GEL file is applied.
    4. Program is loaded and you can stop on start with proper breakpoint (_c_init)
    5. XDC configuration is done for SYSBIOS by program

    Means I was able to stop on point 4 and find:

    CM_WKUP_TIMER0_CLKCTRL = 0x00000002 (SPRUH73P - page 1318, incorrect value 0x00030002)
    CM_PER_TIMER2_CLKCTRL = 0x00000002 (SPRUH73P - page 1278, incorrect value 0x00030000)
    CLKSEL_TIMER2_CLK = 0x00000002 (SPRUH73P - page 1375, incorrect value 0x00000001)

    As was mentioned, GEL file is not doing that. Means 'Reset' is loading that values inside.
    This I was already checked yesterday via different debugger and triggering HW reset.

    This leads to conclusion that problem is in Technical Reference Manual of AM335x (SPRUH73P).
    Please can you inform responsible persons to fix that in that document?

    With best regards
    Jiri
  • 0 in reply to Jiri Biel
    TI__Guru**** 170625 points
    Jiri,

    The change request is already submitted by Steve Kipisz in 26-Jun-2018:

    e2e.ti.com/.../2591538

    The AM335x latest TRM is from March-2017, thus the next version will apply this change. Per mine understanding, only CLKSEL_TIMER2_CLK reset value should be changed, while CM_PER_TIMER2_CLKCTRL reset value is correct, but the ROM code is changing it after reset.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 865 points
    Hi Pavel,
    I have different meaning about this issue:

    If the BOOT ROM is changing the reset values on some registers it needs to at the end put all back to reset state.

    or

    The changes which where done by BOOT ROM are very well documented, that developers are not confused.

    Now I don't see any mention about this in TMR. For example now we are discussing DMTIMER2 and DMTIMER0, but we don't know what everything was changed by BOOT ROM. In that case, when it's not described correctly in TRM any developer can't to trust to any reset value mentioned in TRM. And this leads to very important question why we have TRM???

    With best regards
    Jiri