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Original question:

TCI6630K2L: Can 6630K2L work as 1588 master

TCI6630K2L: K2L EVM FPGA GPIO mapping

sumathi m
Intellectual 905 points

Part Number: TCI6630K2L
Other Parts Discussed in Thread: RFSDK,

Hello,

We have designed a LTE enodeb based on K2L EVM.

We have removed FPGA from the design and used external I/O expanders. We require the GPIO pin mapping info from FPGA to K2L GPIO for the control of Marconi AFE7500 for the attached signals.

In RFSDK, where do we need to change the GPIO's for the control.

Regards,

Sumathi

  • 0
    TI__Genius 9065 points
    Hello Sumathi,

    The RFSDK has to connect to the real time 5ms LTE timers, and modify the timing per the UL/DL TDD signals. The EVM uses the FPGA to map AFE7500 GPIO to specific TCI6630 system GPIOs (with the timers).

    If you have taken out the FPGA, you will need to create a new TCI6630K2L timer module internal and route the signals to the proper GPIOs.

    GPIO expanders can set signals to 1 or 0, but not at the time precision needed, internal counter timers need to get to AFE7500.

    The needed AFE7500 GPIO to TCI6630K2L is listed in the RFSDK2 User Guide.

    best regards,
    David Zhou
  • 0 in reply to dzhou
    Intellectual 905 points

    Hello David,

    Thanks for the support.

    We will implement the timer module.

    currently we are getting Framer error during Device initialization of a custom RF transceiver.

    We are able to read the device ID, but we are observing framing error.

    Is there something missing other than the timer module, since we are not using FPGA, IS the code / RFSDK expecting some inputs?? 

    When we plug the same RF transceiver card on K2L EVM, we do not see any error.. The test is passing.

    But with our K2L board, we get framing error.

    We have used external SPI based I/O expanders. We have interfaced all the signals to/from FPGA to on board BMC (we are using TIVA processor) and shared with SPI I/O expander. Kindly advice whether we are missing something important. We are working on this for more than 2 weeks, so we cross checked the clocks, sync signals etc. The clocks (DEVCLK & SYSREF) are a.c coupled. and seems to be OK similar to K2L EVM. Kindly advice..

    Regards,

    Sumathi

  • 0 in reply to sumathi m
    TI__Genius 9065 points

    Sumathi,

    Device Initialization - typically involves the SPI ports, and the JESD204B lanes.

    The SPI port you can check with RFSDK2 commands.

    The JESD204B port, typically involves problems with Serdes, JESD Sync, and clocking.

    The JESD204B initialization, involves matching the parameters L M F S HD, the RFSDK2 is specifically set For AFE7500.  The AFE7500 has custom settings, in that the Receiver and Transmitter have different values.

    Things that you need to look at:

    The AFE7500 EVM had lane reversals 3<->0, 2<->1.  

    You needs to compare the AFE7500 EVM with the custom RF Transceiver module,

       122.88Mhz Clock

       SPI (there is one set for AFE7500, and one set for Clock)

       Lane pinout

       JESD Sync In

       JESD Sync Out

       GPIO

    JESD204B initialization involves getting through the debugging guide.  

    There is also a DFE GEL file, that goes with the JESD204B troubleshooting

      122.88Mhz clock OK

      JESD Sync In and Sync Out LVDS are OK

      JESD Serdes pass quality tests - this needs special HPA test scripts, not included in RFSDK2

      Look at the JESD troubleshooting guide and the GEL file

         All of the JESD204B errors need to be fixed, or the Rx is zero.

    The RFSDK2 has initialization of Serdes, IQN2, and DFE.   In this initialization, if the JESD204 status is bad, or if the DFE-JESD FIFOs have

    Errors, the initialization has to be redone.   The JESD Debugging Guide has the JESD204b portion.

    Please check the attached file.

    /cfs-file/__key/communityserver-discussions-components-files/791/2047.Lamarr_5F00_JESD_5F00_Debugging_5F00_Guide.pdf

    /cfs-file/__key/communityserver-discussions-components-files/791/4657.DFE2d.gel

    /cfs-file/__key/communityserver-discussions-components-files/791/read_5F00_marconi0_5F00_jesd_5F00_regs.sh

    /cfs-file/__key/communityserver-discussions-components-files/791/read_5F00_lamarr_5F00_jesd_5F00_regs.sh

    best regards,

    David Zhou

  • 0 in reply to dzhou
    Intellectual 905 points

    Hi David,

    Thanks for the reply.

    We’re using a K2L Evaluation board (Device-TCI6630K2L).

    With this, we use a radio transceiver in 4 lane JESD configuration. 

    The issue is “We are not able to get the spectrum using compiled code on mpmcl or in playback mode”. 

    We are using the configurations as follows:

                                         etc\radio\use-case\2x2-4xLTE20-SC-JESD1-HD

    Kindly let us know if something is missing from the configuration settings.

    Regards,

    Sumathi

  • 0 in reply to sumathi m
    Intellectual 905 points
    Hi David,
    We have designed a LTE enodeB based on K2L EVM. We have an issue, the JESD 4 lanes are swapped at the FMC connector. Means the JESD0 is not connecting to JESD0 on the other side of FMC connector. Kindly let me know whether this will cause an issue while configuring for 4 lanes and 2 lanes in RFSDK. How do we go about solving this problem kindly advice. Need more clarity on Rx JESD lanes, which lanes are getting used for Rx and feedback paths.
    We are using the below mentioned files from RFSDK
    2x2-2xLTE20-SC-JESD3b-SD
    2x2-4xLTE20-SC-JESD1-HD

    In your previous mail you have mentioned "The AFE7500 EVM had lane reversals 3<->0, 2<->1. "
    And on our Board also there is JESD Lanes swapping issue.
    In RFSDK can we do the correct mapping??

    Regards,
    Sumathi
  • 0 in reply to sumathi m
    TI__Genius 9065 points
    Hello Sumathi,

    In the RFSDK there are several different pieces that have to load for RFSDK2 to work.

    a) board file - points to specific drivers for AFE7500, your use of SPI for AFE7500, and SPI for clock device has to be the same.

    b) radio select, and configurations files - there are a set of patches needed to get the M1 file to work.
    board
    radio select
    use-case
    playback program
    IQN2 configuration
    Serdes configuration
    Dfe tgtcfg
    (afe7500 library)

    The RFSDK supports configurations with 2 lanes mostly In the DFE tgtcfg listed in the use case files.
    Name_JESD3B_SD.tgtcfg - used JESD lanes 0,1 Name_JESD3B_SD_Lane23.tgtcfg - normally used with 2nd FMC connector used JESD lanes 2,3 (special using rev1 EVM) Name_JESD3B_SD_Lane03.tgtcfg - old EVM version

    Name4x4_JESD3b - uses both FMCs 0,1 lanes first FMC, 2,3 lanes second FMC.

    Name(JESD1)_HD - this uses the first FMC connector all 4 lanes, was only for special test.

    Unless the your custom board matches the AFE7500 lane assignment, the standard RFSDK2 files will not work. You would have to follow modifying the radio select and use case files from the RFSDK2 user guide.

    best regards,
    David Zhou