RTOS/AM5728: How to realize reset of PCIe base specification

Hi,

>>>>>Because it takes much time to reach & run Link Training program through SBL from boot after reset releasing.>>>>>>>The SBL in TI Processor SDK RTOS only supports MMCSD, QSPI and EMMC boot. There is no PCIE initialization and link training code inside, did you customer add this themselves?

What media (SD or QSPI) they used to store the PCIE code and boot from?

- Are there any way to run Link Training before SBL running after reset releasing?>>>>> The ROM bootloader loads and runs the SBL. I need to check the boot time for each different boot media.

Regards, Eric

Our automotive team has created a IEEE article on booting automotive application to acknowledge CAN response and start rear view camera system in 50 ms on this device using SBL which you can find here:
www.researchgate.net/.../301709499_Boot_time_optimization_techniques_for_automotive_rear_view_camera_systems

However, we need to evaluate internally if the PCIE usecase can be successfully met on AM572x given the PMIC solution and the RBL doesn`t support PCIE booting.

Hi,

Thank you very much for your kindness.
I really appreciate your help.

We understand like below;
- More investigation is needed.
- In automotive case, it takes 50ms to run SBL.

So, we are waiting for next update to realize to meet this 20ms requirement by using AM572x
including successful use-case of other customer project by using PCI-Express.

Best regards,

Hi,

Thank you very much for your kindness.
I really appreciate your help.
I'd like to send the answer to the customer.

Best regards,

Part Number: AM5728

Tool/software: TI-RTOS

Hello, TI Experts,

 

Our customer sent us the additional questions from the below E2E-thread.

https://e2e.ti.com/support/processors/f/791/t/790003

 

Could you tell us the detail connection about your suggestion for PERSTn signal like below?

   - The suggestion to delay the PERSTn signal so it can allow SBL on A15 to come up to meet this 20 ms spec requirement.

 

We found the clue to change circuit about REFCLK from RC to EP for TI-EVM such as TMDXIDK5728.

https://e2e.ti.com/support/processors/f/791/t/653443

 

But we cannot found the proper information about PERSTn signal of PCIE-connector on the TMDXIDK5728 using as EP.

 

Question:

   Could you tell us the proper AM5728 pin for PERSTn signal connection?

 

Our customer said like below;

- They didn't find the proper information or document about how to modify the TMDXIDK5728 using as EP.

- And, they connected to PERSTn signal to PORZn of AM572x by logically OR like below at that time.

       " (PMIC → PMIC_RESET_OUTn or PERSTn) → PORZn"

- So, your suggestion seems not to work for their implementation to meet the 20ms PCIE requirement.

- They expect TI send us the some information about the PCIE real product or successful implementation by using AM572x as EP such as PCIE-card for PC-slot.

So, Please tell us the proper connection of PERSTn signal to AM5728 pin.

They try to consider to change PERSTn signal connection of their board design based on your guide.

 

Best regards,

I asked our EVM team to comment on this.

Regards, Eric

Hi Matusan,
The TMDXIDK5728 was designed to operate as a RC and not as an EP. There isn't an easy way to modify the board to operate in EP mode. We don't have a design that implements the AM5728 as RC to provide as an example. There are a number of things to consider with your design.
First, most PCIE system expect the RC to accept the PCIE_RCLK from the PCIE connector. If the EP is using a spread spectrum clock source, connecting that clock to the AM5728 is required for proper operation.
Second, as was highlighted in earlier posts, the AM5728 will not boot quickly enough to enter the LTSSM Detect state in 20msec. This prevents the connection of the PERSTn directly to the POR of the AM5728. A number of solutions have been discussed but, again, we don't have an example. One solution would be to boot the AM5728 on the RC board as soon as the power to the board is present. The PERSTn signal could be connected to an interrupt on the AM5728 which would signal the SoC when the bus is released from reset. Since the AM5728 is powered immediately, it could be ready to enter LTSSM Detect state as soon as the PERSTn is released. The RC must ensure that the PERSTn was not released until after a sufficient amount of time has passed and the AM5728 is ready to react.
Regards, Bill

Hi,

Thank you very much for your kindness.

I really appreciate your help.

I will send the answer to the customer.

Best regards,