RTOS/AM5746: i870 PCIe Eratta

Hi,

The aligned access reads at 32-bit address boundary, like offset 0x0, 0x4, 0x8, 0xc .... In your non-aligned access, you reads at bytes offset 0x1, 0x2 and 0x3. The issue is that Access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields.

When you use workaround 2, This will make all Read TLPs 32-bit aligned with all byte enables set to 1.

In the PCIE TLP, there are relevant fields for this:
- The Length field: indicating number of one DW (32-bit word) of data.
- Address filed [31:2], so this address must be 32-bit aligned
- The 1st BE field (1st Double-Word Byte Enable) allows to choose which of the four bytes in the first data DW are valid

Let's say in your non-alignment access, you want to read offset 0x1 for 8-bit:
- Then you have a TLP with length field 1 indicating 32-bit read,
- address is aligned to 0x0 (instead of 0x1) and
- 1st BE field with 0xF indicating read all 4 bytes (instead of byte 1 only)
So this will return a 32-bit read at aligned 32-bit address.

If you have 3 reads at offset 0x1, 0x2 and 0x3 each with a byte, it will come with 3 TLPs each with 32-bit aligned read and 4 bytes. From PCIE point of view, this is the correct operation and just like you read an aligned address repeated 3 times, it is not a slow down. From your application view, you may think the read is not efficient and slow down.

Is there anything wrong other than slowdown when we took WORKARROUND 2? >>>>From Mukul's earlier reply: The main impact of workaround 2. is that you can’t read just a single byte from the PCIe link partner. This could be an issue if a read of one of the other three bytes of the register you accessing automatically kicks off some event in the link partner.

Regards, Eric