RTOS: EVMK2H with Mistral RTM BOC Rev D and EVMC6657 Hyperlink example for tirtos with problem (not working)

I use SDK 05.02.00.10

BR

Dario

Hi Yordan,

   I have spent a big part of yesterday (and tomorrow) to try to use the same ccs&pdk version for c6657 and k2h, but it is not possible build a c6657 application in h2k environment, then I have tried to use for CC6657 the relative old packages (already installed a couple of year ago):

CrossCompiler tool TI 8.1.0 (CCStudio 6.1.3.00034)
bios_6_46_01_38
pdk_c665x_2_0_4
xdctools_3_32_00_06_core

and for k2h the following versions:

CrossCompiler tool TI 8.2.4 (CCStudio 8.2.0.00007 )
bios_6_73_00_12
pdk_k2hk_4_0_11
xdctools_3_50_08_24_core

Only the SYS/BIOS and PDK are used.

The HLink demo is the demo present in pdk_k2hk_4_0_11, I have configured no xDMA and no ISR demo with 4 Lanes at 3.125GB/s

I have also added a sw platform custom to have uart prints specific for DSP&PDK version.

I have used a C6657 version stored in flash (NOR) using ibl (as nor bootloader), the source files used are:

hyplnk.cmd
hyplnk_device.c
hyplnkExample.c
hyplnkLLDCfg.h
hyplnkLLDIFace.c
hyplnkLLDIFace.h
hyplnkPlatCfg.h
hyplnkResource.c
hyplnkResource.h
memoryMappedExample.cfg

Only hyplnk_device.c is different because on k2H we have a couple of HL channels and one in other board.

The demo stored in a couple of C6657 evm boards work but on mixed connection (C6657&K2H) not work (as reported at my previous ticket).

C6657:

IBL version: 1.0.0.17+
IBL: Booting from NOR

Ext. DDR Init status: 40000004
Ext. DDR Init OK status=0x1
EVAL SW Ver 0.1.1 Build 18 CPU Freq 1000 MHz DSP's core 1 of 2
DSP hw rev. 0 DSP name "TMS320C6657" Board Name "TMDXEVM6657L"Version #: 0x02010006; string HYPLNK LLD Revision: 02.01.00.06:Mar 28 2017:14:26:03
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c4a5; TX=0x000ccfa5
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
  Raw    = 0x4e901900
Status register contents:
  Raw        = 0x00000004
Link status register contents:
  Raw       = 0x00000000
Control register contents:
  Raw             = 0x00000000
Control register contents:
  Raw        = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up (       0)
SERDES_STS (32 bits) contents: 0x03460f1f; lock = 1
Waiting for other side to come up (       1)
Waiting for other side to come up (       2)
Waiting for other side to come up (       3)

.....

K2H:

Eval SW Ver 0.1.1 Build 18 CPU Freq 983 MHz DSP's core 1 of 8
DSP hw rev. 0 DSP name "TCI6636K2H" Board Name "TMDXEVM6636K2H"Version #: 0x02010008; string HYPLNK LLD Revision: 02.01.00.08:Oct  6 2018:02:57:41
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
  Raw    = 0x4e902101
Status register contents:
  Raw        = 0x00003004
Link status register contents:
  Raw       = 0x00000000
Control register contents:
  Raw             = 0x00000000
Control register contents:
  Raw        = 0x00000000
============== end registers before initialization ===========
Hyperlink Serdes Common Init Complete   <------- blocked here

The cfg file is:

var Memory          = xdc.useModule('xdc.runtime.Memory');
var BIOS               = xdc.useModule('ti.sysbios.BIOS');
var Task                = xdc.useModule('ti.sysbios.knl.Task');
var hlink = xdc.useModule('ti.drv.hyplnk.Settings');
var devType = "c6657"; // or "k2h"
hlink.deviceType = devType;
var Csl = xdc.useModule('ti.csl.Settings');
Csl.deviceType = devType;
Csl.useCSLIntcLib = true;
Program.sectMap[".text"]  = "MSMCSRAM";
Program.sectMap[".const"] = "MSMCSRAM";
Program.sectMap[".init_array"] = "L2SRAM";
Program.sectMap[".csl_vect"] = "L2SRAM";
Program.stack = 1024*4 + 0x400;
Program.sectMap[".bss:hyplnkData"] = new Program.SectionSpec();
Program.sectMap[".bss:hyplnkData"].loadAddress=0x830000;
Program.sectMap[".bss:testData"] = "L2SRAM";
Program.sectMap[".bss:QMSSData"] = new Program.SectionSpec();
Program.sectMap[".bss:QMSSData"].loadAddress=0x850000;
Program.sectMap[".bss:packetData"] = new Program.SectionSpec();
Program.sectMap[".bss:packetData"].loadAddress=0x870000;


Program.sectMap["platform_lib"]         = "L2SRAM";
Program.sectMap["systemHeap"]  = "L2SRAM";

var HeapMem                = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams          = new HeapMem.Params();
heapMemParams.size         = 0x3D000;
heapMemParams.sectionName  = "systemHeap";
Program.global.heap0       = HeapMem.create(heapMemParams);
Memory.defaultHeapInstance = Program.global.heap0;

All the other .c and .h files (in hyperliink demo code) are the same in both configurations.

Regards,

Dario

HL_K2H_C6657.zip
There are the ccs projects used for test.

BR

Dario

Hi Yordan,

  first all thank you for your support.

I use a couple of external XDS100_V3 (because the XDS100_V1s are broken when I have attempt to update them using a linux host)
and I use emulator configuration file adapted for recognize their serial number.
When I use a couple of C6657 board I use write the application in NOR to avoid reconfigure SN in configuration file.
But this is not a big problem becouse this configuration (a couple of evm c6657) works.

I prefeir not use a new pdk version on c6657 becouse I have already installed it for an old project.
If you have only the C6678 I think it could be used in a test becouse I think the problem is in K2H side.

I have also requested at Mistral a bit support to assure us that K2H/RTMBOC is used in their test.

Best regards,
Dario

Hi,

I use a couple of external XDS100_V3 (because the XDS100_V1s are broken when I have attempt to update them using a linux host)
and I use emulator configuration file adapted for recognize their serial number.

Do you mean that the onboard XDS emulators of your K2H EVMs won't work?

Best Regards,
Yordan

Hi,

I'm sorry for my mistake, is the XDS200 plugin that not work (for the wrong update procedure), my XDS100V3 is most quick respect on board emulator then I use the external emulator.

BR,
Dario

Hi,

It is good to know that K2H, C6657 loopback mode worked. And C6657 to C6657 also worked. Do you have 2 K2H EVM and 2 BOC card to verify the K2H to K2H also worked?

The failure can be either hardware or software. For the software, typical reason is the data rate doesn't match. For the C6657, or C6678 or K2H the Hyperlink IP is the same. C6657 and C6678 has the same Serdes, but K2H serdes is different. The typical test between K2H and C66x we run is 3.125Gbps or 6.25Gbps, x4 lanes. In the past we verified Hyperlink between C6678 and K2H and we have custom product with this. The Hyperlink example code hasn't been changed for several years, so you use different CCS/SYSBIOS/PRSDK releases on different sides shouldn't matter.

One important thing to check before you trying to access remote side is looking at register offset 0x58, it should be 0xFDF0BDF0, if you use x4 lanes and lanes are not inverted. If this status is not right (e.g Link status register contents: Raw = 0xccf00cf0), the remote access will lock up the whole system.

For the C6657 EVM, the Hyperlink reference clock is 250MHz. I ran the example to check the PLL setting:

When 3.125Gbps: Constructed SERDES configs: PLL=0x00000064; RX=0x0046c4a5; TX=0x000ccfa5
By decoding this: See Hyperlink user guide: 3.4 HyperLink SerDes Configuration and Status Registers
MPY is 12.5, RX and TX are quarter rate, it looked correct for me. (250 * 12.5 *1 = 3.125)

When 6.25 Gbps: Constructed SERDES configs: PLL=0x00000064; RX=0x0046c495; TX=0x000cc315
MPY is still 12.5, RX and TX are half rate, it looked correct for me. (250 * 12.5 *2 = 6.25)

Why in your log:
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c495; TX=0x000cc795
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c4a5; TX=0x000ccfa5

It looked that you have different setting than the original code?

On the K2H side, I looked at the code:
#elif defined hyplnk_EXAMPLE_SERRATE_06p250
linkRate = CSL_SERDES_LINK_RATE_6p25G;
lane_rate = CSL_SERDES_LANE_FULL_RATE;
#elif defined hyplnk_EXAMPLE_SERRATE_03p125
linkRate = CSL_SERDES_LINK_RATE_6p25G;
lane_rate = CSL_SERDES_LANE_HALF_RATE;

This is right.

So my suggestions:
1) If you have two K2H+BOC, please verify that Hyperlink worked to rule out hardware issue
2) For the K2H ---- C6657, please try the 3.125Gbps x 4 as the starting point. Just use the standard Hyperlink test example, but change the hyplnkLLDCfg.h:

#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG

/*****************************************************************************
* Select internal loopback or use the SERDES connection
*****************************************************************************/
////////////#define hyplnk_EXAMPLE_LOOPBACK

/*****************************************************************************
* Select number of lanes allowed
*****************************************************************************/
//#define hyplnk_EXAMPLE_ALLOW_0_LANES
//#define hyplnk_EXAMPLE_ALLOW_1_LANE
#define hyplnk_EXAMPLE_ALLOW_4_LANES

/*****************************************************************************
* Select a serial rate
*****************************************************************************/
//#define hyplnk_EXAMPLE_SERRATE_01p250
#define hyplnk_EXAMPLE_SERRATE_03p125
//#define hyplnk_EXAMPLE_SERRATE_06p250
//#define hyplnk_EXAMPLE_SERRATE_07p500
//#define hyplnk_EXAMPLE_SERRATE_10p000
//#define hyplnk_EXAMPLE_SERRATE_12p500

Then send me the CCS console log on both side. You also can use CCS JTAG to check the hyperlink offset 0x58 value. 3.2.18 Link Status Register (Base Address + 0x58).

You may set a breakpoint in the code (to avoid read remote side and lock up) and dump the Hyperlink register from offset 0x0 to 0x7c to me using CCS memory save (NOTE, just open a small CCS memory window for above register range. Open a bigger one crossing 0x80 will read into remote side and can lock the system if Hyperlink is not really came up).

Regards, Eric

Hi Eric,

I have taken (again) my zipfile (saved on previous thread) some days ago to replicate the same test.
I have captured the following info&logs:

Configuration:

#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG
#define hyplnk_EXAMPLE_ALLOW_4_LANES
#define hyplnk_EXAMPLE_SERRATE_03p125
#define hyplnk_EXAMPLE_ASYNC_CLOCKS
#define hyplnk_EXAMPLE_EQ_ANALYSIS
//#define hyplnk_EXAMPLE_LOOPBACK
//#define enableEDMA
//#define infraDMA
//#define hyplnk_EXAMPLE_ERROR_INTERRUPT



A) first Test: C6657 <---> C6657

C6657(core0) XDS100_V3 (debug)
EVAL SW Ver 0.1.1 Build 18 CPU Freq 1000 MHz DSP's core 1 of 2
DSP hw rev. 0 DSP name "TMS320C6657" Board Name "TMDXEVM6657L"
Version #: 0x02010006; string HYPLNK LLD Revision: 02.01.00.06:Mar 28 2017:14:26:03
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c4a5; TX=0x000ccfa5
system setup worked
....
=== HyperLink results using CPU transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 7115 Mcycles
Approximately 108571 cycles per round-trip
=== this is not an optimized example ===
Checking statistics
Hyperlink LLD Example Completed Successfully!


C6657(core0) (NOR)
EVAL SW Ver 0.1.1 Build 18 CPU Freq 1000 MHz DSP's core 1 of 2
DSP hw rev. 0 DSP name "TMS320C6657" Board Name "TMDXEVM6657L"
Version #: 0x02010006; string HYPLNK LLD Revision: 02.01.00.06:Mar 28 2017:14:26:03
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c4a5; TX=0x000ccfa5
system setup worked
...
=== HyperLink results using CPU transfers ===
Passed 65536 tokens round trip (read+write through hyplnk) in 7115 Mcycles
Approximately 108571 cycles per round-trip
=== this is not an optimized example ===
Checking statistics
Hyperlink LLD Example Completed Successfully!



B) second Test: K2H(core0) <---> C6657(core0) (same configuration)

K2H:
Eval SW Ver 0.1.1 Build 18 CPU Freq 983 MHz DSP's core 1 of 8
DSP hw rev. 0 DSP name "TCI6636K2H" Board Name "TMDXEVM6636K2H"
Version #: 0x02010008; string HYPLNK LLD Revision: 02.01.00.08:1
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
  Raw    = 0x4e902101
Status register contents:
  Raw        = 0x00003004
Link status register contents:
  Raw       = 0x00000000
Control register contents:
  Raw             = 0x00000000
Control register contents:
  Raw        = 0x00000000
============== end registers before initialization ===========
Hyperlink Serdes Common Init Complete  <---- Blocked here.


I'd like to show this section code (on K2H side):

    printf("Hyperlink Serdes Common Init Complete\n"); <---- done
    serdes_lane_enable_params.iteration_mode = CSL_SERDES_LANE_ENABLE_LANE_INIT;
    for(i=0; i< serdes_lane_enable_params.num_lanes; i++)
    {
        serdes_lane_enable_params.lane_mask = 1<<i;
        lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params);  <---- Blocked here.
        if (lane_retval != 0)  <---- Not reached here
        {
            printf ("Invalid Serdes Lane Enable Init %d\n", lane_retval);
            exit(0);
        }
        printf("Hyperlink Serdes Lane %d Init Complete\n", i); <---- The next print should to be this
    }

The infinite loop is here (csl_serdes2.h):

static inline void CSL_SerdesWaitForSigDet(uint32_t base_addr, uint32_t lane_num)
{
    uint32_t retval = 0;
    while(retval != 1)
    {
        retval = (CSL_SERDES_STATUS)CSL_FEXTR(*(volatile uint32_t *)  <---- looped here.
                  (base_addr + 0x1ff4), (0 + lane_num), (0 + lane_num));
    }
}




on C6657 NOR:
EVAL SW Ver 0.1.1 Build 18 CPU Freq 1000 MHz DSP's core 1 of 2
DSP hw rev. 0 DSP name "TMS320C6657" Board Name "TMDXEVM6657L"
Version #: 0x02010006; string HYPLNK LLD Revision: 02.01.00.06:Mar 28 2017:14:26:03
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000064; RX=0x0046c4a5; TX=0x000ccfa5
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
  Raw    = 0x4e901900
Status register contents:
  Raw        = 0x00000004
Link status register contents:
  Raw       = 0x00000000
Control register contents:
  Raw             = 0x00000000
Control register contents:
  Raw        = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up (       0)
SERDES_STS (32 bits) contents: 0x03460f1b; lock = 1
Waiting for other side to come up (       1)
Waiting for other side to come up (       2)
Waiting for other side to come up (       3)
.....
Waiting for other side to come up (     202)
Waiting for other side to come up (     203)
Waiting for other side to come up (     204)
.....

I can give you the dump register, but there are fethed after the infinite loop is arrived, not as you
have suggested before to send any data (I suppose that the serdes aren't configured well).

I hope you can help us to solve thsi problem.

I have only one RTM/BOC board then now I am try to run two demo (almost ;-) ) on two cores on K2H board:
 1)  the first one start the demo immediatly on HL1
 2)  the second one use HL0 (after boot the system) under command (via my Command line)
        start the second demo.
 3)  The cable use Port0 and Port1 connectors as in external loop test configuration.

This test is not finished yet (I have some problem with the printout), the first run seems is done with success
(is it posible thath the lane on HL connector were mapped in different way respect C6657?
I don't know, Mistral not respond at my request).

Best regards,

Dario

Hi,

The C6657 side 3.125Gbps x 4 looks correct. On the K2H, your code snippet explained the problem. After the C6657 side enables the Hyperlink, there should be signal detected on the K2H Serdes level and got PLL lock. But this never happened and Serdes initialization stuck there and waiting forever. The Hyperlink cable should be OK. But I have no idea if the RTM BOC still works or not.

When the Serdes stuck, there is no further Hyperlink initialization on K2H side, you can see that register 0x4 showing bit 0 = 1, that is Hyperlink interface is in reset status.

If you tried the both Hyperlink port 0 and port 1 on K2H side, and saw the same Serdes code stuck. You may look into Hyperlink Serdes register:

Port 0, base address: 0x 0231 A000
Port 1, base address: 0x 0231 C000

Look at offset (refer to www.ti.com/.../spruho3a.pdf Table 16-2. Memory Mapping for PHY-A 4 Lane Sub-Systems)
0x1FE0 LANE1CTL_STS Lane 1 Control and status Section 17.4.1
0x1FE4 LANE2CTL_STS Lane 2 Control and status Section 17.4.1
0x1FE8 LANE3CTL_STS Lane 3 Control and status Section 17.4.1
0x1FEC LANE4CTL_STS Lane 4 Control and status Section 17.4.1
0x1FF4 PLL_CTRL PLL Control Section 17.4.2

to decode. This may give you some clue which lane (or all lanes) has problem.

Regards, Eric

Hi,

Have you got chance to narrow down the Serdes issue?

Regards, Eric

Hi Eric,

     two days ago I have checked that both the HL channels in external loop (using HL5CABLE) on K2H&RTMBOC
works well (two different DSP cores with same HL application "custom" demo) but the same application on
K2H&C6657 configuation not pass at remote register access.

For this test I had used a my custom demo, with the  following changes:

1) it configures the specific channel (becouse the original demo has hardcoded the HL channel HL0/PORT0),
2) I have done some changes to support several times the test without a system reboot needs.

At the startup my "customized" demo configure HL1 (core1) and the same demoapplication running on core0 when the
system boot is finished via Command Line use/configure HL0.

The my "customized" demo configure HL0 on K2H (core0) and the same demo running on C6657 (core0) not arrives
to read/write remote register (the serdes seems working enought well) and both cores goes in "hung"

Follow the HL module used in my custom demo.

hlPart.zip

Serial Log on C6657:

PROMPT:> hlStartTest 0
00:00:53 00:00:53 HyperLinkMain.c@218:  Configure HL0 for loop test
PROMPT:>
00:00:53 00:00:00 hyplnkMemoryMapped.c@735:     Version #: 0x02010006; string HYPLNK LLD Revision: 02.01.00.06:Mar 28 2017:146
00:00:53 00:00:00 hyplnkMemoryMapped.c@746:     About to do system setup (PLL, PSC, and DDR)
00:00:53 00:00:00 hyplnkLLDIFace.c@1037:        Constructed SERDES configs: PLL=0x00000250; RX=0x0046c495; TX=0x000ccf95
00:00:53 00:00:00 hyplnkMemoryMapped.c@753:     system setup worked
00:00:53 00:00:00 hyplnkMemoryMapped.c@761:     About to set up HyperLink Peripheral
00:00:53 00:00:00 hyplnkLLDIFace.c@1607:        ============================
00:00:53 00:00:00 hyplnkLLDIFace.c@1608:        Hyperlink Testing Port 0
00:00:53 00:00:00 hyplnkLLDIFace.c@1609:        ============================
00:00:53 00:00:00 hyplnkLLDIFace.c@1621:        ============== begin registers before initialization ===========
00:00:53 00:00:00 hyplnkLLDIFace.c@606: Revision register contents:  Raw    = 0x4e901900
00:00:53 00:00:00 hyplnkLLDIFace.c@655: Status register contents:  Raw        = 0x00000004
00:00:53 00:00:00 hyplnkLLDIFace.c@698: Link status register contents:  Raw       = 0x00000000
00:00:53 00:00:00 hyplnkLLDIFace.c@729: Control register contents:  Raw             = 0x00000000
00:00:53 00:00:00 hyplnkLLDIFace.c@751: Control register contents:  Raw        = 0x00000000
00:00:53 00:00:00 hyplnkLLDIFace.c@1627:        ============== end registers before initialization ===========
00:00:54 00:00:01 hyplnkLLDIFace.c@1817:        Waiting for other side to come up (       0)
00:00:54 00:00:00 hyplnkLLDIFace.c@840: SERDES_STS (32 bits) contents: 0x03070c19; lock = 1
00:00:54 00:00:00 hyplnkLLDIFace.c@790: VUSR_CFGPLL HyperLink SerDes PLL Configuration: 0x00000250
00:00:54 00:00:00 hyplnkLLDIFace.c@791: VUSR_CFGRX0 HyperLink SerDes Receive Configuration 0 : 0x0046c495
00:00:54 00:00:00 hyplnkLLDIFace.c@792: VUSR_CFGTX0 HyperLink SerDes Transmit Configuration 0: 0x000ccf95
00:00:54 00:00:00 hyplnkLLDIFace.c@793: VUSR_CFGRX1 HyperLink SerDes Receive Configuration 1 : 0x0046c495
00:00:54 00:00:00 hyplnkLLDIFace.c@794: VUSR_CFGTX1 HyperLink SerDes Transmit Configuration 1: 0x000ccf95
00:00:54 00:00:00 hyplnkLLDIFace.c@795: VUSR_CFGRX2 HyperLink SerDes Receive Configuration 2 : 0x0046c495
00:00:54 00:00:00 hyplnkLLDIFace.c@796: VUSR_CFGTX2 HyperLink SerDes Transmit Configuration 2: 0x000ccf95
00:00:54 00:00:00 hyplnkLLDIFace.c@797: VUSR_CFGRX3 HyperLink SerDes Receive Configuration 3 : 0x0046c495
00:00:54 00:00:00 hyplnkLLDIFace.c@798: VUSR_CFGTX3 HyperLink SerDes Transmit Configuration 3: 0x000ccf95
00:00:54 00:00:00 hyplnkLLDIFace.c@808: Chip Version contents: 0x0000b97a
00:00:54 00:00:00 hyplnkLLDIFace.c@810: Lane Power Management Control contents: 0x07070004
00:00:54 00:00:00 hyplnkLLDIFace.c@812: SerDes Control and Status 1 contents: 0xffff0000
00:00:54 00:00:00 hyplnkLLDIFace.c@814: SerDes Control and Status 2 contents: 0x00000000
00:00:54 00:00:00 hyplnkLLDIFace.c@816: SerDes Control and Status 3 contents: 0x00000000
00:00:54 00:00:00 hyplnkLLDIFace.c@818: SerDes Control and Status 4 contents: 0x00000000
00:00:54 00:00:00 hyplnkLLDIFace.c@820: Link Status contents: 0x00000000
00:00:55 00:00:01 hyplnkLLDIFace.c@1817:        Waiting for other side to come up (       1)
00:00:56 00:00:01 hyplnkLLDIFace.c@1817:        Waiting for other side to come up (       2)
00:00:57 00:00:01 hyplnkLLDIFace.c@1817:        Waiting for other side to come up (       3)
00:00:58 00:00:01 hyplnkLLDIFace.c@840: SERDES_STS (32 bits) contents: 0x01020409; lock = 1
00:00:58 00:00:00 hyplnkLLDIFace.c@790: VUSR_CFGPLL HyperLink SerDes PLL Configuration: 0x00000250
00:00:58 00:00:00 hyplnkLLDIFace.c@791: VUSR_CFGRX0 HyperLink SerDes Receive Configuration 0 : 0x0046c495
00:00:58 00:00:00 hyplnkLLDIFace.c@792: VUSR_CFGTX0 HyperLink SerDes Transmit Configuration 0: 0x000ccf95
00:00:58 00:00:00 hyplnkLLDIFace.c@793: VUSR_CFGRX1 HyperLink SerDes Receive Configuration 1 : 0x0046c495
00:00:58 00:00:00 hyplnkLLDIFace.c@794: VUSR_CFGTX1 HyperLink SerDes Transmit Configuration 1: 0x000ccf95
00:00:58 00:00:00 hyplnkLLDIFace.c@795: VUSR_CFGRX2 HyperLink SerDes Receive Configuration 2 : 0x0046c495
00:00:58 00:00:00 hyplnkLLDIFace.c@796: VUSR_CFGTX2 HyperLink SerDes Transmit Configuration 2: 0x000ccf95
00:00:58 00:00:00 hyplnkLLDIFace.c@797: VUSR_CFGRX3 HyperLink SerDes Receive Configuration 3 : 0x0046c495
00:00:58 00:00:00 hyplnkLLDIFace.c@798: VUSR_CFGTX3 HyperLink SerDes Transmit Configuration 3: 0x000ccf95
00:00:58 00:00:00 hyplnkLLDIFace.c@808: Chip Version contents: 0x0000b97a
00:00:58 00:00:00 hyplnkLLDIFace.c@810: Lane Power Management Control contents: 0x07070004
00:00:58 00:00:00 hyplnkLLDIFace.c@812: SerDes Control and Status 1 contents: 0xffff0000
00:00:58 00:00:00 hyplnkLLDIFace.c@814: SerDes Control and Status 2 contents: 0x00000000
00:00:58 00:00:00 hyplnkLLDIFace.c@816: SerDes Control and Status 3 contents: 0x00000000
00:00:58 00:00:00 hyplnkLLDIFace.c@818: SerDes Control and Status 4 contents: 0x00000000
00:00:58 00:00:00 hyplnkLLDIFace.c@820: Link Status contents: 0xccf00cff
00:00:58 00:00:00 hyplnkLLDIFace.c@1838:        ============== begin registers after initialization ===========
00:00:58 00:00:00 hyplnkLLDIFace.c@655: Status register contents:  Raw        = 0x04400005
00:00:58 00:00:00 hyplnkLLDIFace.c@698: Link status register contents:  Raw       = 0xccf00cff
00:00:58 00:00:00 hyplnkLLDIFace.c@729: Control register contents:  Raw             = 0x00004000
00:00:58 00:00:00 hyplnkLLDIFace.c@1842:        ============== end registers after initialization ===========
00:00:58 00:00:00 hyplnkMemoryMapped.c@768:     Peripheral setup worked
00:00:58 00:00:00 hyplnkLLDIFace.c@1912:        Waiting 5 seconds to check link stability
00:01:03 00:00:05 hyplnkLLDIFace.c@1928:        Link seems stable
00:01:03 00:00:00 hyplnkLLDIFace.c@1930:        About to try to read remote registers <<<< blocked here

Serial Log on K2H:

PROMPT:> hlStartTest 0
00:00:45 00:00:45 HyperLinkMain.c@218:  Configure HL0 for loop test

PROMPT:> 00:00:45 00:00:00 hyplnkMemoryMapped.c@735:    Version #: 0x02010008; string HYPLNK LLD Revision: 02.01.00.08:Oct  6
2018:02:57:41
00:00:45 00:00:00 hyplnkMemoryMapped.c@746:     About to do system setup (PLL, PSC, and DDR)
00:00:45 00:00:00 hyplnkLLDIFace.c@1037:        Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
00:00:45 00:00:00 hyplnkMemoryMapped.c@753:     system setup worked
00:00:45 00:00:00 hyplnkMemoryMapped.c@761:     About to set up HyperLink Peripheral
00:00:45 00:00:00 hyplnkLLDIFace.c@1607:        ============================
00:00:45 00:00:00 hyplnkLLDIFace.c@1608:        Hyperlink Testing Port 0
00:00:45 00:00:00 hyplnkLLDIFace.c@1609:        ============================
00:00:45 00:00:00 hyplnkLLDIFace.c@1621:        ============== begin registers before initialization ===========
00:00:45 00:00:00 hyplnkLLDIFace.c@606: Revision register contents:  Raw    = 0x4e902101
00:00:45 00:00:00 hyplnkLLDIFace.c@655: Status register contents:  Raw        = 0x00003004
00:00:45 00:00:00 hyplnkLLDIFace.c@698: Link status register contents:  Raw       = 0x00000000
00:00:45 00:00:00 hyplnkLLDIFace.c@729: Control register contents:  Raw             = 0x00000000
00:00:45 00:00:00 hyplnkLLDIFace.c@751: Control register contents:  Raw        = 0x00000000
00:00:45 00:00:00 hyplnkLLDIFace.c@1627:        ============== end registers before initialization ===========
00:00:45 00:00:00 hyplnkLLDIFace.c@533: Hyperlink Serdes Common Init Complete
00:00:45 00:00:00 hyplnkLLDIFace.c@559: Hyperlink Serdes Lane 0 Init Complete
00:00:45 00:00:00 hyplnkLLDIFace.c@559: Hyperlink Serdes Lane 1 Init Complete
00:00:45 00:00:00 hyplnkLLDIFace.c@559: Hyperlink Serdes Lane 2 Init Complete
00:00:45 00:00:00 hyplnkLLDIFace.c@559: Hyperlink Serdes Lane 3 Init Complete
00:00:45 00:00:00 hyplnkLLDIFace.c@1838:        ============== begin registers after initialization ===========
00:00:45 00:00:00 hyplnkLLDIFace.c@655: Status register contents:  Raw        = 0x04400005
00:00:45 00:00:00 hyplnkLLDIFace.c@698: Link status register contents:  Raw       = 0xccf00cff
00:00:45 00:00:00 hyplnkLLDIFace.c@729: Control register contents:  Raw             = 0x00004000
00:00:45 00:00:00 hyplnkLLDIFace.c@1842:        ============== end registers after initialization ===========
00:00:45 00:00:00 hyplnkMemoryMapped.c@768:     Peripheral setup worked
00:00:45 00:00:00 hyplnkLLDIFace.c@1912:        Waiting 5 seconds to check link stability
00:00:49 00:00:04 hyplnkLLDIFace.c@1928:        Link seems stable
00:00:49 00:00:00 hyplnkLLDIFace.c@1930:        About to try to read remote registers <<<< blocked here

After debugging pause the follow popup appear on ccstudio 8 (K2H):

after debugging pause the follow popup appear on ccstudio 6 (C6657) :

The following function is latest demo application function called (k2h side):

void hyplnkExampleCheckOneStat(int HLPort, hyplnkLocation_e location,
                               const char *name, int noWarn)
{
  int                       pass = 1;
  Hyplnk_Handle             handle = NULL;
  hyplnkRegisters_t         regs;
  hyplnkStatusReg_t         status;
  hyplnkECCErrorsReg_t      ECCErrors;
  const char               *locStr;
  static uint32_t           lastRemoteCor = 0, lastLocalCor = 0;
  uint32_t                 *lastCor;

  memset(&regs, 0, sizeof(regs));
  regs.ECCErrors = &ECCErrors;
  regs.status    = &status;

  if (location == hyplnk_LOCATION_LOCAL)
  {
    locStr  = "Local";
    lastCor = &lastLocalCor;
  }
  else
  {
    locStr  = "Remote";
    lastCor = &lastRemoteCor;
  }

  if (Hyplnk_open(HLPort, &handle) != hyplnk_RET_OK)
  {
    DBG_PRINTF("Open failed");

    return; /* exit(1);*/
  }

  if (Hyplnk_readRegs(handle, location, &regs) != hyplnk_RET_OK)  <<<< here the last called application function.

handle = 0x21400000
location = hyplnk_LOCATION_REMOTE

The next (and latest function called) seems be:

static hyplnkRet_e hyplnk_read_status_reg
(
  CSL_VusrRegs      *baseAddr,
  hyplnkStatusReg_t *reg
)
{
  uint32_t val = reg->raw = baseAddr->STS;

  hyplnk_getbits(val, CSL_VUSR_STS_SWIDTHIN,               reg->swidthin); <<<< here the last called line function before crash.

I have forced the selected file becouse the ccs try to open (without succes) for arm/cortex version instead a DSP version (correct one):

Follow the Histral answer.

/////////////// Mistral answer Start /////////////

Hi Dario,

Hyperlink interface should work with TI EVM-K2H evaluation board. We have tested Hyperlink interface between
boards using below cable. There is no jumper/resistor settings required for configuration.

https://www.ti.com/store/ti/en/p/product/?p=HL5CABLE 

Please refer the attachment & below link for more details.

http://software-dl.ti.com/processor-sw/esd/PROCESSOR-SDK-RTOS-K2HK/latest/index_FDS.html 

Feel free to write to evmsupport@mistralsolutions.com for any clarifications.  Thanks