RTOS/AM5746: About the PCIe byte enable

rei

Mastermind 6155 points

Part Number: AM5746

Tool/software: TI-RTOS

Hi.
It is a question related to the previous E2E. Please look at this pdf file.

e2e.pdf

We can choose which of the 4 bytes to enable in The 1st BE field.

Question 1:
If it reads the above data to a variable(RD), what kind of data will it be?(1 or 2)

Question 2:
Would you tell me how to set 1st BE field.

Regards,
Rei

over 7 years ago

0 lding over 7 years ago

TI__Guru* 95265 points

Rei,

From Errata i870:
To workaround this issue, there are two options:
1. Avoid issuing read accesses to the PCIe slave port that are not 32-bit aligned
2. Set the PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLE bits to 0x1 in the
CTRL_CORE_SMA_SW_7 Control Module register. This will make all Read TLPs 32-
bit aligned with all byte enables set to 1.

If you use the choice 2, all the 4 bytes in TLP 1st BE field are enabled. You don't have control to enable a certain byte. Your read will return all 4 bytes with 32-bit aligned (although you intend to read only a certain byte).

Regards, Eric

0 rei over 7 years ago in reply to lding

Mastermind 6155 points

Hi Eric,
thank you as always.

How is it read if you don't set Workaround 2 (do not set the PCIE_SSx_AXI2OCP_LEGACY_MODE_ENABLE bit: use Workaround 1)?

Regards,
Rei

0 lding over 7 years ago in reply to rei

TI__Guru* 95265 points

Hi Rei,

If you don't use workaround 2, then you need to use workaround 1: Avoid issuing read accesses to the PCIe slave port that are not 32-bit aligned.

This is controlled from your application code, you always do a PCIE read with 32-bit aligned address (e.g, offset 0x0, 0x4, 0x08, 0xC ....).

Regards, Eric

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RTOS/AM5746: About the PCIe byte enable