Part Number: EVMK2GX
Tool/software: Code Composer Studio
Hi,
I'm using code composer to develop an application using the QSPI peripheral using indirect transfer oo the EVMK2GX. Code is below when performing a QSPIWriteFifoData the entire application crashes when attempting to copy the data into the SRAM located at 0x24000000 also if I try to read the memory region using the debugger memory browser it states that it cannot read it. Obviously there is something I am missing and could be beyond within the project settings themselves. Any direction pointing will be helpful.
QSPIDisable(QSPI_0_CFG_REGS);
QSPIDacDisable(QSPI_0_CFG_REGS);
UT_ASSERT_DIE(0 == QSPIWaitIdle(QSPI_0_CFG_REGS));
QSPISetClkMode(QSPI_0_CFG_REGS, QSPI_CLK_MODE_0);
uint32_t devDelays[4] = {
QSPI_DEV_DELAY_CSSOT, /* default Chip Select Start of Transfer Delay */
QSPI_DEV_DELAY_CSEOT, /* default Chip Select End of Transfer Delay */
QSPI_DEV_DELAY_CSDADS, /* default Chip Select De-Assert Different Slaves Delay */
QSPI_DEV_DELAY_CSDA /* default Chip Select De-Assert Delay */
};
QSPISetDevDelay(QSPI_0_CFG_REGS, devDelays);
QSPISetChipSelect(QSPI_0_CFG_REGS, QSPI_CHIP_SELECT_CS0, QSPI_DECODER_SELECT4);
QSPISetPreScaler(QSPI_0_CFG_REGS, QSPI_BAUD_RATE_DIVISOR_DEFAULT);
QSPILoopbackDisable(QSPI_0_CFG_REGS);
QSPISetDevSize(QSPI_0_CFG_REGS,
QSPI_MEM_MAP_NUM_ADDR_BYTES_THREE,
512,
16);
QSPISetIndTrigAddr(QSPI_0_CFG_REGS, QSPI_0_DATA);
QSPISetWrCompAutoPolling(QSPI_0_CFG_REGS, QSPI_WRITE_COMP_AUTO_POLLING_DISABLE);
QSPISetSramPartition(QSPI_0_CFG_REGS, QSPI_SRAM_PARTITION_DEFAULT);
QSPIIntrDisable(QSPI_0_CFG_REGS, QSPI_INTR_MASK_ALL);
QSPIIntrClear(QSPI_0_CFG_REGS, QSPI_INTR_MASK_ALL);
QSPIEnable(QSPI_0_CFG_REGS);
//Actual Test Area
uint8_t testWrData[4];
testWrData[0] = 0xDE;
testWrData[1] = 0xAD;
testWrData[2] = 0xCA;
testWrData[3] = 0xFe;
uint8_t *pSrc = &testWrData[0];
uint8_t testRdData[4] = {0x00, 0x00, 0x00, 0x00};
uint8_t *pDst = &testRdData[0];
uint32_t count = 4;
/* Setup indirect write transfer */
QSPIIndWriteSetup(QSPI_0_CFG_REGS, 0, NOR_CMD_QUAD_PAGE_PROG /*?TODO Device Specific?*/, QSPI_XFER_LINES_QUAD/*TODO typedef top of code*/);
QSPIIndWriteExecute(QSPI_0_CFG_REGS, count);
/* Wait Indirect Write SRAM fill level below the threshold */
uint32_t sramLevel;
UT_ASSERT_DIE(0 == QSPIWaitWriteSramLvl(QSPI_0_CFG_REGS, &sramLevel));
uint32_t remaining = count;
while(remaining > 0)
{
/* Wait indirect write SRAM fifo level below watermark */
UT_ASSERT_DIE(0 == QSPIWaitWriteSramLvl(QSPI_0_CFG_REGS, &sramLevel));
uint32_t wrBytes = (QSPI_SRAM_PARTITION_WR - sramLevel) * QSPI_FIFO_WIDTH;
wrBytes = wrBytes > remaining ? remaining : wrBytes;
/* Write data to FIFO */
QSPIWriteFifoData(QSPI_0_DATA, pSrc, wrBytes);
pSrc += wrBytes;
remaining -= wrBytes;
}
UT_ASSERT_DIE(0 == QSPIWaitIndWriteComplete(QSPI_0_CFG_REGS));
