RTOS/AM5728: SMP processing on EtherCAT-Master reference design(TIDEP0079)

#include <ti/sysbios/family/arm/a15/Cache.h>

#include <ti/sysbios/family/arm/a15/smp/Cache.h>

/* Add MMU entries for MMR's required for PCIE example */

Mmu_DescriptorAttrs attrs;

extern char ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_0__A;

extern char ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_1__A;

uint32_t addr0 = (uint32_t)&ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_0__A;

uint32_t addr1 = (uint32_t)&ti_sysbios_family_arm_a15_Mmu_Module_State_0_secondLevelTableBuf_1__A;

Mmu_initDescAttrs(&attrs);

attrs.type = Mmu_DescriptorType_TABLE;

attrs.shareable = 0;           // non-shareable

attrs.accPerm = 1;             // read/write at any privelege level

attrs.attrIndx = 0;             // Use MAIR0 Register Byte 3 for

                               // determining the memory attributes

                               // for each MMU entry

// Update the first level table's MMU entry for 0x00000000 with the

// new attributes.

Mmu_setFirstLevelDesc((Ptr)0x00000000, (UInt64)addr0, &attrs);

// Update the first level table's MMU entry for 0x40000000 with the

// new attributes.

Mmu_setFirstLevelDesc((Ptr)0x40000000, (UInt64)addr1, &attrs);

// descriptor attribute structure

var peripheralAttrs1 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(peripheralAttrs1);

peripheralAttrs1.type = Mmu.DescriptorType_TABLE;

peripheralAttrs1.accPerm = 1;                   // read/write at any PL

peripheralAttrs1.shareable = 0;                 // non-shareable

peripheralAttrs1.attrIndx = 0;                   // Use MAIR0 Register Byte 3 for

                                                 // determining the memory attributes

                                                 // for each MMU entry                           Mmu.setFirstLevelDescMeta(0x00000000, 0x80001000, peripheralAttrs1);

Mmu.setFirstLevelDescMeta(0x40000000, 0x80002000, peripheralAttrs1);