Hello,
We are have designed an enodeB based on K2L EVM. We are using common SPI signals (MISO, MOSI and CLK) to both FMC connectors. The reset and Chipselect is different for the two FMC conn. .
The question is, If jesd0 and jesd1 is used from conn 1 and jesd3 and jesd4 is used from conn2, what would be the timing constraints , delay, required for the spi signals communication when transferring the data on both connectors?
What is the SPI timing delay required while switching from one connector to another.??
Regards,
Sumathi
