Linux/AM3352: GPMC timings

Rahul Tungar

Prodigy 50 points

Part Number: AM3352

Tool/software: Linux

Dear team,

I am interfacing dpram with AM335x.

During this i observed two point i need more information on those points.

1> from below figure you can see for read acess(Its from am335x datasheet).

First valid address comes on bus and ALE goes high.

Then cs goes low and ale again high.

Now below image is from trm of am335x and here

first ale goes high with valid data on bus.

Then cs goes low but in this case ale remains high .

can you tell me which one is ok case.

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

Hi,

Both diagrams are correct regarding the address phase of the access cycle. Address is latched on the rising edge of ALE. Signal status before falling edge of CS is irrelevant.

0 Rahul Tungar over 6 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Is their any way to invert ALE signal?

0 Biser Gatchev-XID over 6 years ago in reply to Rahul Tungar

TI__Guru**** 393215 points

Only with external circuitry.

0 Rahul Tungar over 6 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Thank you for your reply.

What i understood is that processor first will out address and make ALE high at same time.

then CS will go low and other signals will proceed.

Is their any way that i processor first will out address on bus and then after say a single cycle make ALE high.

i think in my circuit i am having issue like as processor is loading address on bus and making ALE high in same cycle,

0 Biser Gatchev-XID over 6 years ago in reply to Rahul Tungar

TI__Guru**** 393215 points

This is controlled by the ADVWROFFTIME/ADVRDOFFTIME/ADVONTIME/ADVEXTRADELAY parameters in GPMC_CONFIG3 register. See section 7.1.5.13 in the AM335x TRM Rev. P.

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Linux/AM3352: GPMC timings