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66AK2H12: About Gel file vs Board_init()

SamSeytani
Intellectual 535 points
Part Number: 66AK2H12

Hello,

Could you explain the difference between the GEL file and Board_Init regarding DDR initialization. I noticed that only GEL file initialization is not enough for complete DDR initialization. DDR read speed was very low only with GEL file. When i all Board_init in main function, DDR speed increased very signifacantly.

Why is that happened?

What is the difference between GEL file and Board_init() considering DDR?

Best regards.

  • 0
    TI__Guru** 116020 points

    SamSetyani,

    The GEL and Board_init setting for DDR should exactly be the same, why do you think that the external memory access is slow. 

    GEL is a initialization tool which is typically used for debugging, HW bring up since it can be run over emulator and is easy to debug issue with GEL scripting. When you move to production code, users are expected to use Board_init as you need to do the same initialization using target software which boots from a flash boot media in an end application. 

    The two are designed to be exactly the same. Infact we derive the DDR setting used in board library based on external memory setup that has been tested using the GEL files. You can refer to the article here that describes the board bring up process that we use and recommend to Processor SDK RTOS users.

    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#custom-board-addition

    For GEL setup, can you confirm that you are using the following EVM setup

    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#ak2gx-gp-evm-hardware-setup

    The one thing that you can check is to see if the DDR is set to 800 Mhz or 1066 Mhz. You can drive the DDR PLL to OBSCLK using a GEL setting and connect a scope to measure the clocks.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 535 points

    My problem was about doing memcpy from DDR (0x80000000) to Hyperlink  window. My previous the GEL settings:   ddr3A_64bit_DDR1600_setup()

    ddr3B_64bit_DDR1600_setup()

    Set_Pll1(5) (main pll dsp is 1.22 Ghz)

    The transfer speed was very low when I measure Hyperlink throughput ( about 0.07 Gbps for different data sizes).

    I changed the GEL files ddr3A setting to:   ddr3A_32bit_DDR1333_setup()

    Then the transfer speed dramatically increased up to 5.5 Gbps for 64KB data size.

    What is the reason for that? Is DDR (0x80000000) address belongs to DDR3B? If it is DDR3B than why the modification on the DDR3A changed the speed of my measurement?

    Another question is that what is the default settings in Board_PLLInit() (under evmKeystone/board_pll.c) ? What is the main pll dsp frequency in that case?

    DSP is in no-boot mode

  • 0 in reply to SamSeytani
    TI__Guru** 116020 points

    SamSeytani,

    Can you please indicate where you have obtained the previous GEL settings that you were using? If you look at the GEL provided by TI the default onTarget setting for the device is as follows:

    // Setup main PLL DSP @ 983 MHz
    Set_Pll1(3); // call Set_Pll1 with index = 3 -> 122.88 MHz to 983.04 MHz operation

    // Setup ARM PLL index = 1 -> 125 MHz to 1000 MHz operation
    Set_Tetris_Pll(1);

    GEL_TextOut("DDR begin\n");
    xmc_setup();
    ddr3A_32bit_DDR1333_setup();
    ddr3B_64bit_DDR1600_setup();

    This is what is being used even with board_init settings.

    /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
    Board_STATUS Board_DDR3Init()
    {
    xmc_add_emif_cfg_region();

    CSL_BootCfgUnlockKicker();
    if (init_ddrphy(CSL_DDR3_0_PHY_CFG_REGS, &ddr3phy_1333_32) == false)
    return BOARD_INIT_DDR_FAIL;
    init_ddremif((CSL_Emif4fHandle)CSL_DDR3_0_SLV_CFG_REGS, &ddr3_1333_32);

    if (init_ddrphy(CSL_DDR3_1_PHY_CFG_REGS, &ddr3phy_1600_64) == false)
    return BOARD_INIT_DDR_FAIL;
    init_ddremif((CSL_Emif4fHandle)CSL_DDR3_1_SLV_CFG_REGS, &ddr3_1600_64);

    return BOARD_SOK;
    }

    The board library uses the same PLL setting as in the GEL:

    const pllcConfig pllcConfigs[] = {
    {CSL_PLL_SYS, 16, 1, 2}, /* 983 MHz */   -->   (122.88* 16/2)
    {CSL_PLL_PA, 16, 1, 2}, /* 983 MHz*/
    {CSL_PLL_ARM, 16, 1, 2}, /* 1000 MHz*/
    {CSL_PLL_DDR3, 20, 1, 6}, /* 333 MHz*/
    {CSL_PLL_DDR3B, 16, 1, 4} /* 400 MHz*/
    };

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 535 points

    Sorry for the late response as i was on a holiday.

    The settings are the same as you showed here.

    Surprisingly, when I switched back to GEL file from Board_init(), everything worked fine.

    Regards.