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RTOS/AM5728: DDR configuration

matusan
Guru 10235 points

Part Number: AM5728
Other Parts Discussed in Thread: TMDXIDK5718

Tool/software: TI-RTOS

Hello, TI Experts,

Our customer sent us questions about "how to remove EMIF2-DDR" by using TI-RTOS(PROCESSOR-SDK-RTOS-AM57X). They developed their custom board by removing DDR2 connected to EMIF2 referring TMDXIDK5728. And they try to create their application program by using PROCESSOR-SDK-RTOS-AM57X.

They want to know how to modify "idkAM572x_ddr.c" for removing EMIF2-DDR.

So, they created the "idkAM572x_ddr.c" like below way.

   - They use "idkAM572x_ddr.c".

   - They change "Board_STATUS Board_DDR3Init()" by copy & paste from "idkAM571x_ddr.c".

     (Because TMDXIDK5718 is used only EMIF1-DDR).

Please refer attached pdf file in detail modification.  

Question:

  They said it seems to run properly their custom board with their above modification.

  Is it OK to use for their mass-production product?

We would appreciate if you tell us the proper/successful way of removing EMIF2-DDR including how to modify "idkAM572x_ddr.c". If there are any notice or comment for their modification way such as pasting from " idkAM571x_ddr.c", please also tell us.

 

Best regards,

ddr_cfg.pdf

  • 0
    TI__Guru** 116870 points

    Matusan,

    I have looped in the DDR expert to comment on whether the AM571x DDR setting can be used in AM572x design where only EMIF1 is being used.  I can comment from a software perspective, this seems to be reasonable to leverage the DDR settings for EMIF1 with the DMM LISA Map registers setting this to non-interleaved mode. 

    The other difference that you need to account for is DDR3 supports only upto 1066  MTs on AM572x while DDR3 support for AM571x supports upto 1333 Mts so the timings will be different due to lower speed setting. We recommend that you first generate the DDR settings using the EMIF tools provided here and generate a GEL to validate the settings. 

    http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprac36  (Tool provided generates GEL file after user inputs DDR3 datasheet details)

    Make sure that you have a memory diagnostic test that runs reliably on the custom board  to check out the entire DDR range before deciding to use this setting in a production setup. software recommendation for custom board validation are provided here:
    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#custom-board-validation

    Please review the pointers in my response and wait for further inputs from the DDR expert from our HW team.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.

    I really appreciate your help.

    We are also waiting for the DDR expert feedback.

     

    Best regards,

  • 0 in reply to matusan
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.

    I really appreciate your help.

     

    Now, we are waiting for the DDR expert feedback.

    And we also tried to check the EMIF-Tool output like below;

     

    <EMIF-Tool result>

    static void AM572x_DDR3L_533MHz_TI_AM572x_EVM (uint32_t base_addr)                                

    {                                

       SDRAM_TIM_1 = 0xCEEF2663U;                                

       SDRAM_TIM_2 = 0x308F7FDAU;                                

       SDRAM_TIM_3 = 0x409F88A8U;                                

     

       SDRAM_REF_CTRL = 0x0000103DU;                                

       SDRAM_REF_CTRL_INIT = 0x00004111U;                                

       SDRAM_CONFIG = 0x61862332U;                                

     

       EMIF_PHY_READ_LATENCY = 0xCU;                                

       EMIF_PHY_INVERT_CLKOUT = 0x1U;                                

       EMIF_PHY_HALF_DELAY_MODE = 0x1U;                                

       EMIF_PHY_DQ_OFFSET = 0x40U;                                

       EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U;                                

     

       DISABLE_READ_LEVELING = 0x0U;                                

       DISABLE_READ_GATE_LEVELING = 0x0U;                                

       DISABLE_WRITE_LEVELING = 0x0U;                                

     

       /* EXT_PHY_CTRL_xx are used only in case of HW_LEVELING_ENABLED = 0*/                                

       /* EMIF_PHY_FIFO_WE_SLAVE_RATIO (RD_DQS_GATE) */                                

       EXT_PHY_CTRL_2 = 0x006B006BU;                                

       …

     

    And our understanding for modified idkAM572x_ddr.c of ddr_cfg.pdf is like below;

       SDRAM_TIM_1 = 0xCEEF2663U;         -> apply to ddr3Config1.emifDdrParam.sdramTim1        

       SDRAM_TIM_2 = 0x308F7FDAU;         -> apply to ddr3Config1.emifDdrParam.sdramTim2                        

       SDRAM_TIM_3 = 0x409F88A8U;          -> apply to ddr3Config1.emifDdrParam.sdramTim3

       SDRAM_CONFIG = 0x61862332U;       -> apply to ddr3Config1.emifDdrParam.sdramCfg

     

    Questions:

     -  Are those above understanding correct? 

     - Could you tell us where to apply about below configuration result from EMIF-tool to

       "modified idkAM572x_ddr.c of ddr_cfg.pdf " which we attached previous E2E-post?

       SDRAM_REF_CTRL = 0x0000103DU;

       SDRAM_REF_CTRL_INIT = 0x00004111U;                 

     

       EMIF_PHY_READ_LATENCY = 0xCU;                                

       EMIF_PHY_INVERT_CLKOUT = 0x1U;                                

       EMIF_PHY_HALF_DELAY_MODE = 0x1U;                                

       EMIF_PHY_DQ_OFFSET = 0x40U;                                

       EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U;                                

     

       DISABLE_READ_LEVELING = 0x0U;                                

       DISABLE_READ_GATE_LEVELING = 0x0U;                                

       DISABLE_WRITE_LEVELING = 0x0U;                                

     

       EXT_PHY_CTRL_x (x=2..21)

     

    We appreciate if you tell us how to exactly write the idkAM572x_ddr.c from EMIF-Tool result from the DDR expert feedback.

     

    Best regards,

  • 0 in reply to matusan
    TI__Mastermind 46460 points

    Matusan,

    What is the open hardware question?  AM572x devices have 2 DDR3 EMIF interfaces.  AM571x devices have a single DDR3 EMIF interface.  Both are supported with EMIF configuration tools that are used to generate the hardware configuration values needed to robustly operate with specific SDRAM devices.  If you need help with memory addressing and internal resource mapping from a software perspective, that is not a hardware question.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.

    I really appreciate your help.

     

    Our customer want to know "how to modify "idkAM572x_ddr.c" for removing one EMIF2-DDR of AM572x.

    So we understand this question is related to mainly software.

    Thank you for your feedback.

     

    And we also waiting for the answer below questions in previous our E2E-post. (like software side)

    We would appreciate if proper engineer tell us the answer.

    Questions:

     - Are those above understanding correct? 

     - Could you tell us where to apply about below configuration result from EMIF-tool to

       "modified idkAM572x_ddr.c of ddr_cfg.pdf " which we attached previous E2E-post?

       SDRAM_REF_CTRL = 0x0000103DU;

       SDRAM_REF_CTRL_INIT = 0x00004111U;                 

     

       EMIF_PHY_READ_LATENCY = 0xCU;                                

       EMIF_PHY_INVERT_CLKOUT = 0x1U;                                

       EMIF_PHY_HALF_DELAY_MODE = 0x1U;                                

       EMIF_PHY_DQ_OFFSET = 0x40U;                                

       EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U;                                

     

       DISABLE_READ_LEVELING = 0x0U;                                

       DISABLE_READ_GATE_LEVELING = 0x0U;                                

       DISABLE_WRITE_LEVELING = 0x0U;                                

     

       EXT_PHY_CTRL_x (x=2..21)

    Best regards,

  • 0 in reply to matusan
    TI__Guru** 116870 points

    Matusan,

    Did you communicate the software side comments and inputs AM571x DDR settings were created for higher speed DDR PLL settings with your customer that. 

    If they are using the EMIF tool for the device, were they able to generate a GEL file and test the settings using an emulator before trying to modify the board library? I would request that you compare the GEL and the board_ddr.c to find the mapping.

    Here is the mapping for the ones you have requested above:

    SDRAM_REF_CTRL_INIT maps to hEmif->regs->SDRAM_REFRESH_CONTROL before SDRAM_CONFIG is set

    SDRAM_REF_CTRL maps to hEmif->regs->SDRAM_REFRESH_CONTROL after SDRAM_CONFIG is set

    The following PHY configuration maps to  

    matusan said:

       EMIF_PHY_READ_LATENCY = 0xCU;                                

       EMIF_PHY_INVERT_CLKOUT = 0x1U;                                

       EMIF_PHY_HALF_DELAY_MODE = 0x1U;                                

       EMIF_PHY_DQ_OFFSET = 0x40U;                                

       EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U;    

        /* Fields in DDR_PHY_CTRL_1 */
     /* Bit[21] - calculated using DataMacro/MDLL clock ratio
    * Set to 1 for 532M, so that PHY DLL runs at 266.
    * Set to 0 for 400M, so that PHY DLL runs at 400M.
    * Ensure PHY DLL lower limit of 266M is not violated.
    */
    uint32_t emifPhyHalfDelayMode = 1U;
    uint32_t emifPhyDisCalibRst = 0U;    /* Bit[19]    */
    uint32_t emifPhyInvertClkout = 1U;    /* Bit[18]    */
    uint32_t emifPhyDllLockDiff = 0x10U; /* Bit[17:10] */
    uint32_t emifPhyFastDllLock = 0U;   /* Bit[9]     */
    uint32_t emifPhyReadLatency = 0xBU;  /* Bit[4:0], Typically >= (CL + 4) */

    The rest of the mapping is done as follows:

     DISABLE_READ_LEVELING = 0x0U;  &    DISABLE_WRITE_LEVELING = 0x0U; &   DISABLE_READ_GATE_LEVELING = 0x0U;  

    maps to hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

     EXT_PHY_CTRL_x (x=2..21) maps to hEmif->regs->EXT_PHY_CONTROL_x

     

    Please review the response and let us know if this helps.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 10235 points

    Hi,

    Thank you very much for your detail explanation.

    I really appreciate your help.

     

    We also found below description in idkAM571x_ddr.c.

    - ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;

         -> seems to be related to "EMIF_PHY_DQ_OFFSET = 0x40U;"

    - ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;

         -> seems to be related to "EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U; "

     

    So, from your explanation, our understanding for the answer to the customer is like below;

    - At first, recommended to generate a GEL file and test the settings using an emulator

       before trying to modify the board library.

    - EMIF-Tool output GEL configuration maps to the idkAM571x_ddr.c is like below;

       - SDRAM_TIM_1 -> ddr3Config1.emifDdrParam.sdramTim1

       - SDRAM_TIM_2 -> ddr3Config1.emifDdrParam.sdramTim2

       - SDRAM_TIM_3 -> ddr3Config1.emifDdrParam.sdramTim3

     

       - SDRAM_REF_CTRL_INIT

           -> hEmif->regs->SDRAM_REFRESH_CONTROL=sdRamRefCtrlInit;

       - SDRAM_REF_CTRL

           -> hEmif->regs->SDRAM_REFRESH_CONTROL = ddr3Config->emifDdrParam.sdramRefCtrl;

       - SDRAM_CONFIG -> ddr3Config1.emifDdrParam.sdramCfg

     

       - EMIF_PHY_READ_LATENCY -> emifPhyReadLatency = 0xBU; /* Bit[4:0], Typically >= (CL + 4) */

       - EMIF_PHY_INVERT_CLKOUT -> emifPhyInvertClkout = 1U;   /* Bit[18]   */

       - EMIF_PHY_HALF_DELAY_MODE -> emifPhyHalfDelayMode = 1U; /* Bit[21] */

       - EMIF_PHY_DQ_OFFSET -> ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;

       - EMIF_PHY_CTRL_SLAVE_RATIO -> ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;

     

       - DISABLE_READ_LEVELING -> hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

       - DISABLE_READ_GATE_LEVELING -> hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

       - DISABLE_WRITE_LEVELING -> hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

     

       - EXT_PHY_CTRL_x (x=2..21) maps to hEmif->regs->EXT_PHY_CONTROL_x

       -> We don't touch this values because of below comment in idkAM571x_ddr.c

             "EXT_PHY_CTRL_xx are used only in case of HW_LEVELING_ENABLED = 0"

     

    I also attached "pdf" for the understanding summary.

     

    If there are any miss-understanding point, please tell us.

     

    Best regards,

    idkAM571x_ddr.pdf

  • 0 in reply to Rahul Prabhu
    Guru 10235 points

    Hi,

    Thank you very much for your detail explanation.

    I really appreciate your help.

     

    We also found below description in idkAM571x_ddr.c.

    - ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;

         -> seems to be related to "EMIF_PHY_DQ_OFFSET = 0x40U;"

    - ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;

         -> seems to be related to "EMIF_PHY_CTRL_SLAVE_RATIO = 0x80U; "

     

    So, from your explanation, our understanding for the answer to the customer is like below;

    - At first, recommended to generate a GEL file and test the settings using an emulator

       before trying to modify the board library.

    - EMIF-Tool output GEL configuration maps to the idkAM571x_ddr.c is like below;

       - SDRAM_TIM_1 -> ddr3Config1.emifDdrParam.sdramTim1

       - SDRAM_TIM_2 -> ddr3Config1.emifDdrParam.sdramTim2

       - SDRAM_TIM_3 -> ddr3Config1.emifDdrParam.sdramTim3

     

       - SDRAM_REF_CTRL_INIT

           -> hEmif->regs->SDRAM_REFRESH_CONTROL=sdRamRefCtrlInit;

       - SDRAM_REF_CTRL

           -> hEmif->regs->SDRAM_REFRESH_CONTROL = ddr3Config->emifDdrParam.sdramRefCtrl;

       - SDRAM_CONFIG -> ddr3Config1.emifDdrParam.sdramCfg

     

       - EMIF_PHY_READ_LATENCY -> emifPhyReadLatency = 0xBU; /* Bit[4:0], Typically >= (CL + 4) */

       - EMIF_PHY_INVERT_CLKOUT -> emifPhyInvertClkout = 1U;   /* Bit[18]   */

       - EMIF_PHY_HALF_DELAY_MODE -> emifPhyHalfDelayMode = 1U; /* Bit[21] */

       - EMIF_PHY_DQ_OFFSET -> ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;

       - EMIF_PHY_CTRL_SLAVE_RATIO -> ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;

     

       - DISABLE_READ_LEVELING -> hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

       - DISABLE_READ_GATE_LEVELING -> hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

       - DISABLE_WRITE_LEVELING -> hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;

     

       - EXT_PHY_CTRL_x (x=2..21) maps to hEmif->regs->EXT_PHY_CONTROL_x

       -> We don't touch this values because of below comment in "EMIF-Tool output GEL configuration sheet".

             "EXT_PHY_CTRL_xx are used only in case of HW_LEVELING_ENABLED = 0"

     

    I also attached "pdf" for the understanding summary.

     

    If there are any miss-understanding point, please tell us.

     

    Best regards,

    8054.idkAM571x_ddr.pdf

  • 0 in reply to matusan
    TI__Guru** 116870 points

    Matusan,

    Instead of providing the updated file as PDF, if you could provide the updated .c file and the updated EMIF tool GEL output, we can do a diff with existing source file and GEL files and help confirm the setup. Please request the customer to provide the .c and the updated GEL

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.

    I really appreciate your help.

    I will send the answer to the customer.

     

    Best regards,