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RTOS/TDA2HG: VISION SDK build

user5134010
Intellectual 350 points
Part Number: TDA2HG

Tool/software: TI-RTOS

Hi，

I  have a TDA2XX development board.I want to run the routine under PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\src\hlos\adas\src\usecases.

I compiled two files, MLO and AppImage, according to VisionSDK_UserGuide_TDA2xx.pdf.Start by AD card.

but didn't print any information when I started the board.I have no problem with the compilation process.

Can you give me a print message to start TDA2XX with MLO and AppImage?I want to know what is going to be like this.

I am very grateful that you can help me.

Best Regards,

Abel

  • 0
    TI__Guru 55685 points

    Hi,

    What is the SYSBOOT switch setting?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 350 points

    Hi，

    There is no problem with the SYSBOOT settings, just follow the instructions of VisionSDK_UserGuide_TDA2xx.pdf.

    could you give me a print message to start TDA2XX with MLO and AppImage?I want to make a reference.

    Best Regards,

    ABel

  • 0 in reply to user5134010
    TI__Guru 55685 points

    Hi ABel,

    Please see https://e2e.ti.com/support/processors/f/791/t/818741

    Also note that you are referring to Linux use case and for that you will need to build Linux configuration.

    You should see PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\docs\Linux\VisionSDK_Linux_UserGuide.pdf.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points

    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 350 points

    Hi，

    I am very grateful that you can help me.

    The problem I encountered is similar to  https://e2e.ti.com/support/processors/f/791/t/818741 and my log is：

    >TDA2xx SBL Boot
    >
    > DPLL Configuration Completed
    >
    > Clock Domain Configuration Completed
    >
    > Module Enable Configuration Completed
    >
    > TI EVM PAD Config Completed
    >
    > DDR Config Completed
    >
    > App Image Download Begins
    >
    > SD Boot - file open completed successfully
    >
    > MPU CPU0 Image Load Completed
    >
    > IPU1 CPU0 Image Load Completed
    >
    > IPU1 CPU1 Image Load Completed
    >
    > IPU2 CPU0 and CPU1 Image Load Completed
    >
    > DSP1 Image Load Completed
    >
    > DSP2 Image Load Completed
    >
    > EVE1 Image Load Completed
    >
    > EVE2 Image Load Completed
    >
    > EVE3 Image Load Completed
    >
    > EVE4 Image Load Completed
    >
    > App Image Download Completed
    >
    > Putting MPU CPU1 in Off mode
    >
    > EVE MMU configuration completed
    >
    > EVE MMU configuration completed
    >
    > EVE MMU configuration completed
    >
    > EVE MMU configuration completed
    >
    >*****************************************************************
    >
    > PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles
    >
    > SBL Initial Config Cycles - 141627  (12.8 ms)
    > SOC Init Cycles - 169142  (14.43 ms)
    > DDR Config Clock Cycles - 99245  (8.46 ms)
    > App Image Load Cycles - 93636462  (7990.31 ms)
    > Slave Core Bootup Cycles - 208013  (17.75 ms)
    > SBL Boot-up Cycles - 94255550  (8043.14 ms)
    > Time at which SBL started IPU1_0 - 273177  (23.31 ms)
    >*****************************************************************
    >
    > Jumping to MPU CPU0 App

    I noticed that the code of A15 can run，But the function“ Vps_printf” cannot print out.I added the UARTConfigPuts print, which can output normally.

    The printed result is：

    Jumping to MPU CPU0 App

    A15 main_common 1

    A15 main_common 2

    I think function “ Vps_printf”  does not take effect.，How to solve this problem？

    Best Regards,

    Abel

  • 0 in reply to user5134010
    TI__Guru 55685 points

    Hi Abel,

    In Vision SDK all prints are directed to a remote log buffer and IPU1_0 takes care of printing the logs to UART console.

    User is not supposed to directly access UART via UART driver APIs.

    In case when you use Vps_printf the print will appear somewhere later in the log depending upon the timestamp as multiple CPUs might have written to remote buffer before A15.

    Can you check the complete log to see if you get prints from A15.

    If no please share the log as an attachment.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 350 points

    Hi,

    Thank you for your answer！

    I can't get anyprints from A15 and other cores.My log is added to the payment

    Regards,

    Abel

    Fullscreen RTOS_LOG.txt Download 
    [18:23:19] TDA2xx SBL Boot 
[18:23:19]
[18:23:19] DPLL Configuration Completed 
[18:23:19]
[18:23:19] Clock Domain Configuration Completed 
[18:23:19]
[18:23:19] Module Enable Configuration Completed 
[18:23:19]
[18:23:19] TI EVM PAD Config Completed 
[18:23:19]ERROR: HW-Leveling time-out
[18:23:19]
[18:23:19] DDR Config Completed 
[18:23:19]
[18:23:19] App Image Download Begins 
[18:23:19]
[18:23:19] SD Boot - file open completed successfully 
[18:23:20]
[18:23:20] MPU CPU0 Image Load Completed 
[18:23:22]
[18:23:22] IPU1 CPU0 Image Load Completed 
[18:23:23]
[18:23:23] IPU1 CPU1 Image Load Completed 
[18:23:23]
[18:23:23] IPU2 CPU0 and CPU1 Image Load Completed 
[18:23:24]
[18:23:24] DSP1 Image Load Completed 
[18:23:25]
[18:23:25] DSP2 Image Load Completed 
[18:23:26]
[18:23:26] EVE1 Image Load Completed 
[18:23:26]
[18:23:26] EVE2 Image Load Completed 
[18:23:27]
[18:23:27] EVE3 Image Load Completed 
[18:23:27]
[18:23:27] EVE4 Image Load Completed 
[18:23:27]
[18:23:27] App Image Download Completed 
[18:23:27]
[18:23:27] Putting MPU CPU1 in Off mode 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27]*****************************************************************
[18:23:27]
[18:23:27] PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 
[18:23:27]
[18:23:27] SBL Initial Config Cycles - 141597  (12.8 ms)
[18:23:27] SOC Init Cycles - 169272  (14.44 ms)
[18:23:27] DDR Config Clock Cycles - 99167  (8.46 ms)
[18:23:27] App Image Load Cycles - 92418524  (7886.38 ms)
[18:23:27] Slave Core Bootup Cycles - 208148  (17.76 ms)
[18:23:27] SBL Boot-up Cycles - 93037768  (7939.22 ms)
[18:23:27] Time at which SBL started IPU1_0 - 269191  (22.97 ms)
[18:23:27]*****************************************************************
[18:23:27]
[18:23:27] Jumping to MPU CPU0 App

  • 0 in reply to user5134010
    TI__Guru 55685 points

    Hi Abel,

    This is not the main menu of Vision SDK, these prints are coming from SBL.

    It seems that there is a hang during IPC attach.

    What are the changes that you have made?

    Can you try with prebuilt SDK binary to see the expected output.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points

    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh