RTOS/AM5728: OCMC RAM definition in EtherCAT Master

matusan

Guru 10235 points

Part Number: AM5728
Other Parts Discussed in Thread: TIDEP0079, SYSBIOS

Tool/software: TI-RTOS

Hello, TI Experts,

Our customer sent us questions about "how to add the new memory area of OCMC_RAM2"

with below EtherCAT-Master reference design(TIDEP0079) by using TI-RTOS(PROCESSOR-SDK-RTOS-AM57X).

http://www.ti.com/lit/ug/tidubz1b/tidubz1b.pdf

They would like to add other memory area for their programs to OCMC_RAM2.

But the below CCS project is already configured for EC-Master program in DDR Memory area.

(We also add our test TMDXIDK5728-CCS project as a reference.)

https://www.acontis.com/en/ethercat-for-ti-processors.html

Question:

- Could you tell us how to add the new memory area of OCMC_RAM2 for their new programs?

Best regards,

0537.EcMasterDemoICSS.zip

over 5 years ago

0 Paula Carrillo over 5 years ago

TI__Mastermind 34150 points

Hi Matusan-san, I will check this tomorrow. Sorry for the delay.

A quick question in the meantime, the idea is to change platform definition via CCS? (something similar to what I did for http://www.ti.com/lit/an/sprac45a/sprac45a.pdf chapter4) or this is something else?

thank you,

Paula

0 matusan over 5 years ago in reply to Paula Carrillo

Guru 10235 points

Hi,

Thank you very much for your kindness.

I really appreciate your help.

We checked "RTSC" configuration by "CCS-Menu->Project->RTSC-Tools->Platform->Edit/View"

referring your guide of below pdf (chapter4).

http://www.ti.com/lit/an/sprac45a/sprac45a.pdf

But it seems to be configured only one Memory domain such as EXT_RAM for Code Memory like below.

They would like to add other memory area for their programs to OCMC_RAM2.

So, we are waiting for your checking result including "how to configure both EXT_MEM and OCMC_RAM2 domain for Code Memory"

Best regards,

0 Paula Carrillo over 5 years ago in reply to matusan

TI__Mastermind 34150 points

Hi Matusan-san, is the intention to move critical code closer to CPU? if so, you can modify TI's linker template (*.xdt) file. A similar approach was explored in the DDR-less application note previously shared (section 4.2.2.).

You could also move sections using Program.sectMap[] in your CCS project *.cfg file. See http://www.sanb.design.ti.com/iliad/webhome/xdoc/index.html#xdc/cfg/Program.html#sect.Map for further details. The main idea is that you can "explicitly" place some sections in different memory segments. Whatever is "not explicitly" defined will go to code memory (in this case EXT_RAM).

Finally, If the intention is to increase size of memory, also in TI's linker, you can do something like:

SECTIONS {

.text: > EXT_RAM | OCMC_RAM2

}

which will first place .text into DDR and if/when that fills up, will “spill over” to OCMCRAM.

Hope this helps. Thank you,

Paula

0 matusan over 5 years ago in reply to Paula Carrillo

Guru 10235 points

Hi,

Thank you very much for your detail explanation.

I really appreciate your help.

We checked "sectMap" behavior from your advice by using TI-sample-project "UART_BasicExample_idkAM572x_armExampleProject" like below procedure.

1: add "__attribute__((section("MAIN_SECT")))" to main();

2: add "Program.sectMap["MAIN_SECT"] = "OCMC_RAM2";" & build.

3: We found it seems to run from OCMC_RAM2(0x40400000) properly.

(We also attached related pdf & CCS project as a reference).

Question:

Is this proper way?

If there are any notice or comment to send the answer to the customer, please tell us.

Best regards,

sectmap.pdf

UART_BasicExample_idkAM572x_armExampleProject.zip

0 Paula Carrillo over 5 years ago in reply to matusan

TI__Mastermind 34150 points

Matusan-san, checking shared UART example *.map it looks good to me. You now have MAIN_SECT in OCMC_RAM2 and other *.text (sysbios) in DDR. Good proof of concept =)Thanks for sharing this.

Paula

0 matusan over 5 years ago in reply to Paula Carrillo

Guru 10235 points

Hi,

Thank you very much for your kindness.

I really appreciate your help.

I will send the answer to the customer.

Best regards,

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RTOS/AM5728: OCMC RAM definition in EtherCAT Master