AM5728: Reserving interrupt lines for RTOS jailhouse inmate

Nir Geller

Part Number: AM5728

Hi there,

I'm working with Linux processor-sdk 05.02.00.10 and RTOS processor-sdk 4.03.00.05.
I successfully worked with jailhouse hypervisor on the AM5728 evaluation board.

Now I'm setting up a RTOS jailhouse inmate on a AM5728 based custom board and I'm trying to figure out which irq lines I need to reserve in the Linux kernel dts.

Going through

http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_Virtualization.html

and analyzing ICSS_EMAC example, I see that additional irq's 44 127 129 136 137 are reserved in am572x-idk-jailhouse.dtsi.

I see the interruptNum arguments that are used when the ICSS_EMAC RTOS inmate invokes HwiP_create() is invoked, but there's no connection between them and the numbers skipped in the dts.

Also, nodes in the dts that hold lines like

interrupts = <GIC_SPI xx IRQ_TYPE_LEVEL_HIGH>;

with matching numbers (44 127 129...) are not related to the ICSS_EMAC example.

How can I figure the irq numbers I need to skip for my RTOS app?

Thanks a lot,

Nir.

over 6 years ago

0 Nir Geller over 6 years ago

Expert 1140 points

Does

omapconf dump crossbar irq mpu

help me in any way?

0 Bin Liu over 6 years ago in reply to Nir Geller

TI__Guru**** 167611 points

Hi Nir,

In RTOS SDK v5.0.0.15, the interrupts used in the ICSS_EMAC example are defined in <RTOS-SDK>/pdk_am57xx_1_0_11/packages/ti/drv/icss_emac/test/src/main.c:

513 int32_t ICSS_EMAC_testPruIcssInstance2Setup(void)
514 {
...
552 #ifndef __LINUX_USER_SPACE
553     /* For PRU2 Eth0 */
554     CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_127, CSL_XBAR_PRUSS2_IRQ_HOST8); /* link ISR */
555     CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_137, CSL_XBAR_PRUSS2_IRQ_HOST2); /* RX PKT ISR */
556     CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_129, CSL_XBAR_PRUSS2_IRQ_HOST4); /* TX PKT ISR */
557 #ifndef SWITCH_EMAC
558     if ((ICSS_EMAC_testEvmType == ICSS_EMAC_TEST_BOARD_IDKAM572x) || (ICSS_EMAC_testEvmType == ICSS_EMAC_TEST_BOARD_IDKAM574x))
559     {
560     /* For PRU2 Eth1 */
561         CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_134, CSL_XBAR_PRUSS2_IRQ_HOST9); /* link ISR */
562         CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_135, CSL_XBAR_PRUSS2_IRQ_HOST3); /* RX PKT ISR */
563         CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_136, CSL_XBAR_PRUSS2_IRQ_HOST5); /* TX PKT ISR */
564     }

0 Nir Geller over 6 years ago in reply to Bin Liu

Expert 1140 points

Hi,

Thanks for your reply.

In my system gpio1_3 is used as an interrupt.

GPIO_setConfig_v1() registers the interrupt of gpio1_3 with

interruptRegParam.corepacConfig.intVecNum = hwAttrs->lin1IntNum; == 61

Where is the number 61 coming from?

When GPIO_enableInt() is invoked to enable the interrupt of gpio1_3 I get a nasty error message on the Linux side:

[ 111.304105] irq 0, desc: d4803700, depth: 1, count: 0, unhandled: 0
[ 111.304107] ->handle_irq(): c01807f8,
[ 111.304118] handle_bad_irq+0x0/0x2a4
[ 111.304120] ->irq_data.chip(): c0d1aae4,
[ 111.304127] no_irq_chip+0x0/0x88
[ 111.304130] ->action(): (null)
[ 111.304133] IRQ_NOPROBE set
[ 111.304135] IRQ_NOREQUEST set
[ 111.304138] unexpected IRQ trap at vector 00

This message appears only once.

A new line is added to /proc/interrupts

0: 1 none Edge

The callback function of gpio1_3 is not invoked.

Dumping the crossbar yields this:

ac832d29ed8584666c818727068_code-editor-fs">Fullscreen -filesystemfile/__key/communityserver-discussions-components-files/791/dump_5F00_mpu_5F00_crossbar.txt?_=637007891540000000" ossbar.txt">dump_mpu_crossbar.txt -filesystemfile/__key/communityserver-discussions-components-files/791/dump_5F00_mpu_5F00_crossbar.txt?_=637007891540000000" ossbar.txt">Download 2d29ed8584666c818727068_code-editor" 230px;margin:0px;" (rev v1.73 built Sun Mar 10 11:16:57 UTC 2019) Tree) performance (1.0GHz)) _____ _ _ 20171011 (Linaro GCC 7.2-2017.11 --------------------------------------------------------------------------------------------------------| | --------------------------------------------------------------------------------------------------------| | Source | Description | --------------------------------------------------------------------------------------------------------| | MPU_CLUSTER | Illegal writes to interrupt controller memory map region | | MPU_C0_CS_CTI | TRIGOUT[6] of Cross Trigger Interface 0 (CTI0) | | MPU_C1_CS_CTI | TRIGOUT[6] of Cross Trigger Interface 1 (CTI1) | | MPU_CLUSTER | Error indication for AXI write transactions with a BRESP err | | reserved | N/A | PU_C0_IRQ_WARN | MPU_WD_TIMER | MPU_WD_TIMER channel 0 warning interrupt | PU_C1_IRQ_WARN | MPU_WD_TIMER | MPU_WD_TIMER channel 1 warning interrupt | | reserved | N/A | | reserved | N/A | | reserved | N/A | | L3_MAIN | L3_MAIN application or non-attributable error | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | GPIO2 | GPIO2 interrupt 1 | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | TIMER8 | TIMER8 interrupt | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | reserved | N/A | | I2C5 | I2C5 interrupt | | I2C3 | I2C3 interrupt | | reserved | N/A | | USB2 | USB2 interrupt 0 | | USB1 | USB1 interrupt 0 | | HDMI | HDMI interrupt | | MCSPI2 | McSPI2 interrupt | | reserved | N/A | | reserved | N/A | | reserved | N/A | | DISPC | Display controller interrupt | | VIP2 | VIP2 interrupt 2 | | VIP2 | VIP2 interrupt 1 | | DSP2 | DSP2 MMU1 interrupt | | DSP2 | DSP2 MMU0 interrupt | | VPE | VPE interrupt | | RNG | RNG interrupt | | SHA2MD5_1 | SHA2MD5_1 interrupt on HIB2 | | DES3DES | DES3DES public interrupt | | reserved | N/A | | AES1 | AES1 public interrupt | | BB2D | BB2D interrupt | | GPU | GPU interrupt | | DCAN1 | DCAN1 interrupt 0 | | GMAC_SW | GMAC_SW miscellaneous interrupt | | GMAC_SW | GMAC_SW transmit interrupt | | GMAC_SW | GMAC_SW receive interrupt | Q_RX_THRESH_PULSE | GMAC_SW | GMAC_SW receive threshold interrupt | | USB2 | USB2 interrupt 1 | | USB1 | USB1 interrupt 1 | | RTC_SS | RTC_SS alarm interrupt | | SATA | SATA interrupt | | QSPI | QSPI interrupt | | IPU2 | IPU2 MMU interrupt | | IPU1 | IPU1 MMU interrupt | | DSP1 | DSP1 MMU1 interrupt | | DSP1 | DSP1 MMU0 interrupt | | MMC2 | MMC2 interrupt | | reserved | N/A | | I2C1 | I2C1 interrupt | | DMM | DMM interrupt | | WD_TIMER2 | WD_TIMER2 interrupt | | TIMER16 | TIMER16 interrupt | | TIMER15 | TIMER15 interrupt | | TIMER14 | TIMER14 interrupt | | TIMER13 | TIMER13 interrupt | | TIMER12 | TIMER12 interrupt | | TIMER11 | TIMER11 interrupt | | TIMER10 | TIMER10 interrupt | | TIMER9 | TIMER9 interrupt | | TIMER7 | TIMER7 interrupt | | TIMER6 | TIMER6 interrupt | | TIMER5 | TIMER5 interrupt | | TIMER4 | TIMER4 interrupt | | TIMER3 | TIMER3 interrupt | | MAILBOX6 | Mailbox 6 user 3 interrupt | | MAILBOX6 | Mailbox 6 user 2 interrupt | | MAILBOX6 | Mailbox 6 user 1 interrupt | | MAILBOX6 | Mailbox 6 user 0 interrupt | | MAILBOX5 | Mailbox 5 user 3 interrupt | | MAILBOX5 | Mailbox 5 user 2 interrupt | | MAILBOX5 | Mailbox 5 user 1 interrupt | | MAILBOX5 | Mailbox 5 user 0 interrupt | | UART10 | UART10 interrupt | | GPIO8 | GPIO8 interrupt 1 | | GPIO7 | GPIO7 interrupt 1 | | GPIO6 | GPIO6 interrupt 1 | | reserved | N/A | | GPIO4 | GPIO4 interrupt 1 | | reserved | N/A | | GPIO3 | GPIO3 interrupt 1 | | MPU_CLUSTER | MPU core 0 PMU interrupt | | MPU_CLUSTER | MPU core 1 PMU interrupt | | reserved | N/A | | PRU_ICSS2 | PRU-ICSS2 host interrupt 3 (AM57xx only) | | PRU_ICSS2 | PRU-ICSS2 host interrupt 4 (AM57xx only) | | PRU_ICSS2 | PRU-ICSS2 host interrupt 5 (AM57xx only) | | PRU_ICSS2 | PRU-ICSS2 host interrupt 6 (AM57xx only) | | GPIO2 | GPIO2 interrupt 1 | | reserved | N/A | | reserved | N/A | | GPIO1 | GPIO1 interrupt 1 | | EDMA | TC1 EDMA TPTC1 error interrupt | | EDMA | TC0 EDMA TPTC0 error interrupt | | EDMA | TPCC EDMA TPCC error interrupt | | EDMA | TPCC EDMA TPCC memory protection interrupt | | EDMA | TPCC EDMA TPCC region 0 interrupt | | DMA_SYSTEM | System DMA interrupt 3 | | DMA_SYSTEM | System DMA interrupt 2 | | DMA_SYSTEM | System DMA interrupt 1 | | DMA_SYSTEM | System DMA interrupt 0 | E_CORE_IRQ_THERMAL_ALERT | CTRL_MODULE | CTRL_MODULE thermal alert interrupt | | PCIe_SS1 | PCIe_SS1 interrupt 1 | | reserved | N/A | | reserved | N/A | | PCIe_SS1 | PCIe_SS1 interrupt 0 | | reserved | N/A | | PRM | PRCM interrupt to MPU | | L3_MAIN | L3_MAIN debug error | | TIMER1 | TIMER1 interrupt | --------------------------------------------------------------------------------------------------------| -1a84591e31034fac832d29ed8584666c818727068_code-editor-fs'); 91e31034fac832d29ed8584666c818727068_code-editor'); function(){ tor('fullscreen')) { tor('fullscreen', false); tor('fullscreen', true);

If I understand correctly, GPIO1_IRQ_1 is directed by crossbar 24 to MPU_IRQ 141. Is this correct?

I tried setting interruptRegParam.corepacConfig.intVecNum to 141 but got the same result.

If I skip 141 in the kernel dts am572x-idk-jailhouse.dtsi, GPIO1_IRQ_1 is set to MPU_IRQ 144 instead.

Should I skip any specific irq number in the dts?

With regard to inmate cell configuration, what irq number in irqchips needs to be passed to the inamte to make gpio1_3 interrupt trigger the RTOS inmate instead of the Linux?

Thanks a lot,

Nir.

0 Bin Liu over 6 years ago in reply to Nir Geller

TI__Guru**** 167611 points

Nir,

Nir Geller said:

When GPIO_enableInt() is invoked to enable the interrupt of gpio1_3 I get a nasty error message on the Linux side:

[ 111.304105] irq 0, desc: d4803700, depth: 1, count: 0, unhandled: 0
[ 111.304107] ->handle_irq(): c01807f8,
[ 111.304118] handle_bad_irq+0x0/0x2a4
[ 111.304120] ->irq_data.chip(): c0d1aae4,
[ 111.304127] no_irq_chip+0x0/0x88
[ 111.304130] ->action(): (null)
[ 111.304133] IRQ_NOPROBE set
[ 111.304135] IRQ_NOREQUEST set
[ 111.304138] unexpected IRQ trap at vector 00

First of all, please ensure you have disabled gpio1 in your Linux device tree, similar to gpio2, gpio3, or gpio5 am572x-idk-jailhouse.dtsi.

0 Nir Geller over 6 years ago in reply to Bin Liu

Expert 1140 points

After disabling gpio1 in the dts the kernel doesn't dump the error message.

But the ISR is still not invoked and I didn't get answers to any of my questions.

Where is the number 61 coming from?

What is the meaning of intVecNum? is it the MPU_IRQ index?

Should I skip any specific irq number in the dts?

With regard to inmate cell configuration, what irq number in irqchips needs to be passed to the inamte to make gpio1_3 interrupt trigger the RTOS inmate instead of the Linux?

Thanks a lot,

Nir.

0 Bin Liu over 6 years ago in reply to Nir Geller

TI__Guru**** 167611 points

Nir,

Nir Geller said:

After disabling gpio1 in the dts the kernel doesn't dump the error message.

But the ISR is still not invoked and I didn't get answers to any of my questions.

Please let's solve problems one by one. If a forum post has too much information, it either leads to the wrong direction of the debug, or readers got confused.

For your rest of RTOS related questions, I will direct them to other software expert to help.

0 Garrett Ding over 6 years ago in reply to Bin Liu

TI__Mastermind 43296 points

Nir,

The number 61 is the GIC ID Number, see TRM Table 17-2. MPU_INTC Default Interrupt Mapping, MPU_IRQ_29 (ID61), and the footprint - This column shows the association between the Shared Peripheral Interrupts (MPU_IRQ_0 – MPU_IRQ_159) and the GIC inputs (ID32 – ID191).

There is an offset 32 between MPU_IRQ and GIC input.

The below line in the dump_mpu_crossbar.txt indicates the GPIO1 interrupt (input number 24) is routed by cross bar configuration register at 0x4A002B52, i.e. CTRL_CORE_MPU_IRQ_140_141[24:16], to MPU_IRQ_141 (ID173).

>> 141 | 0x4A002B52 | 24 | GPIO1_IRQ_1 | GPIO1 | GPIO1 interrupt 1

then intVecNum should be set to 173.

Regards,

Garrett

0 Nir Geller over 6 years ago in reply to Garrett Ding

Expert 1140 points

Hi Garrett,

After disabling GPIO1 and skipping irq 29 in am572x-idk-jailhouse.dtsi the crossbar is configured as follows

29 | 0x4A002A76 | 24 | GPIO1_IRQ_1 | GPIO1 | GPIO1 interrupt 1

I added irq 29 to the inmate cell configuration and now I'm getting GPIO1 interrupt in the RTOS side.

Thanks for your help,

Nir.

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AM5728: Reserving interrupt lines for RTOS jailhouse inmate