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66AK2H12: Regarding DSP L2 cache register (MAR)

Kz777
Expert 7895 points
Part Number: 66AK2H12

Hi Champs,

The following document mentioned

TMS320C66x DSP CorePac User Guide. 4.5 Memory Attribute Register (MARn) Definition defined Bit 2-1（PCX and WTE） as Reserved

Also, we recognized these bit ( Bit 2（PCX）or 1（WTE）) value difference affect to active time. So, it affect some device function.  

And also current MARn default value is Bit2 (PCX) = '1'. Bit1 (WTE) ='0'.

【Question ①】

Could you please tell us correct value for MAR setting ?

If we would like to enable MAR effectively , do we have to set  '1' for Bit 0 (PC) and Bit 3 (PFX) it mean 0x9 ?

As our experience, 0x09 setting is very fast , 0xD or 0xF is very slow.

Accourding to TMS320C66x DSP CorePac User GuideのTable 4-22 , this Bit 0(PC) initial value =0.

However, when we confirm debugger memory view MAR register , this MAR register for Bit0 (PC) is 1 or 0 on the setMar().

Also, according this URL TMS320C66x DSP CorePac User Guide show opposite opinion. 

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/sysbios/6_41_04_54/exports/bios_6_41_04_54/docs/cdoc/ti/sysbios/family/c66/Cache.html#.P.C.X

"The 'pc' ("Permit Caching") field is enabled for all memory regions in the device platform. Only set the fields of the Mar structure which need to be modified. Any field not set retains its reset value."

Could you please tell us  this default value Bit0 (PC) 1 or 0, or expressly set or undefined value ? 

Could you please answer this correct value  between TMS320C66x DSP CorePac User Guide and above link consistency and consider Bit2 and Bit 1 affection  ?

Regards,

Kz777

  • 0
    TI__Guru* 95265 points

    Hi,

    You may look at below E2E for further discussion:

    e2e.ti.com/.../267700
    e2e.ti.com/.../333040
    e2e.ti.com/.../590641


    MAR register Bits:
    Bit 0: PC, Permit copies field enables/disables the cacheability of the affected address range.
    Bit 1: WTE (Undocumented), enabling/disabling write-through caching mode for the region
    Bit 2: PCX (Undocumented), enabling/disabling an external memory (from CorePac perspective) as a cache
    Bit 3: PFX, Enables/disables the prefetchability of the affected address range.

    At the default setting: 

    • MSMC region is 0xD
    • DDR region is 0xC

    If you want to enable MAR effectively, you can set it as 0xD. I didn't see any usage setting it as 0x9. From above E2E discussions, I thought BIT 2 = "1" or "0" shouldn't matter.

    For the default PC bit value, I connected to DSP core without GEL file in no-boot mode. For the MSMC region, the PC = 1. For the DDR region, PC  = 0.

    Regards, Eric