Tool/software: Linux
Hi,
The previous thread has not been resolved, By mistake it was attended as resolved.
On running the debug clock scipt, I get the following, provided the device tree endpoint in dss tda19988_in is commented out.
=====================DSS clock script=================== Dumps internal clocks and muxes of DSS CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AB video1 PLL : Disabled video2 PLL : Disabled HDMI PLL : Enabled DSI1_A_CLK mux : DPLL HDMI DSI1_B_CLK mux : DPLL video2 DSI1_C_CLK mux : DPLL Video1 DSS_CTRL (0x58000040) = 0x00000000 2: LCD1 clk switch : DSS clk 3: LCD2 clk switch : DSS clk 10: LCD3 clk switch : DSS clk 1: func clk switch : DSS clk 13: DPI1 output : HDMI DSS_STATUS (0x5800005C) = 0x01408A81 DSI_CLK_CTRL (0x58004054) = 0x00000001 CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040B03 CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00000702 ======================================================== Register dump for DPLL hdmi |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x58040200 | 0x00000018 | | 0x58040204 | 0x00000003 | | 0x58040208 | 0x00000000 | | 0x5804020C | 0x0004A40E | | 0x58040210 | 0x00602004 | | 0x58040214 | 0x00001800 | | 0x58040218 | 0x00000000 | | 0x5804021C | 0x00000000 | | 0x58040220 | 0x00080000 | |----------------------------| Details for DPLL hdmi PLL status : Locked M4 hsdiv(1) : inactive M5 hsdiv(2) : inactive M6 hsdiv(3) : inactive M7 hsdiv(4) : inactive PLL_REGM = 594 PLL_REGN = 7 M4 DIV = 0 M6 DIV = 0 M7 DIV = 0 PLL_REGM2 = 2 PLL_REGM_F = 2 PLL_SD = 6 HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000 HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000 Clock calculations (DPLL hdmi) sysclk = 20000000 CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000 ======================================================== Clock O/P of MUXes DPLL PER H12 Output 192000000 CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204 DSI1_A_CLK : 742500000 DSI1_B_CLK : 0 DSI1_C_CLK : 0 DISPC_DIVISOR (0x58001804) = 0x00010001 2: LCD1 clk : 192000000 3: LCD2 clk : 192000000 10: LCD3 clk : 192000000 1: func clk : 192000000 LCD1 logic clk(/ 1 ) : 192000000 pix clk(/ 2 ) : 96000000 LCD2 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000 LCD3 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 4800000
When the dpi_out endpoint is made as lcd_out by giving a dummy lcd panel node, I get the following result,
=====================DSS clock script=================== Dumps internal clocks and muxes of DSS CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A2 video1 PLL : Enabled video2 PLL : Disabled HDMI PLL : Enabled DSI1_A_CLK mux : DPLL Video1 DSI1_B_CLK mux : DPLL video2 DSI1_C_CLK mux : DPLL Video1 DSS_CTRL (0x58000040) = 0x00010001 2: LCD1 clk switch : DSI1_A_CLK 3: LCD2 clk switch : DSS clk 10: LCD3 clk switch : DSS clk 1: func clk switch : DSS clk 13: DPI1 output : LCD1 DSS_STATUS (0x5800005C) = 0x01408A82 DSI_CLK_CTRL (0x58004054) = 0x80004001 CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040F03 CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00001702 ======================================================== Register dump for DPLL video1 |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x58004300 | 0x00000018 | | 0x58004304 | 0x00002F83 | | 0x58004308 | 0x00000000 | | 0x5800430C | 0x252AA44E | | 0x58004310 | 0x02E56008 | | 0x58004314 | 0x00000129 | | 0x58004318 | 0x00000000 | | 0x5800431C | 0x00000000 | | 0x58004320 | 0x00000000 | |----------------------------| Details for DPLL video1 PLL status : Locked M4 hsdiv(1) : Active M5 hsdiv(2) : Active M6 hsdiv(3) : Active M7 hsdiv(4) : Active PLL_REGM = 1362 PLL_REGN = 39 M4 DIV = 9 M6 DIV = 9 M7 DIV = 9 Clock calculations (DPLL video1) sysclk = 20000000 DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1362000000 M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 136200000 M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 136200000 M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 136200000 ======================================================== Register dump for DPLL hdmi |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x58040200 | 0x00000018 | | 0x58040204 | 0x00000003 | | 0x58040208 | 0x00000000 | | 0x5804020C | 0x0004A40E | | 0x58040210 | 0x00602004 | | 0x58040214 | 0x00001800 | | 0x58040218 | 0x00000000 | | 0x5804021C | 0x00000000 | | 0x58040220 | 0x00080000 | |----------------------------| Details for DPLL hdmi PLL status : Locked M4 hsdiv(1) : inactive M5 hsdiv(2) : inactive M6 hsdiv(3) : inactive M7 hsdiv(4) : inactive PLL_REGM = 594 PLL_REGN = 7 M4 DIV = 0 M6 DIV = 0 M7 DIV = 0 PLL_REGM2 = 2 PLL_REGM_F = 2 PLL_SD = 6 HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000 HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000 Clock calculations (DPLL hdmi) sysclk = 20000000 CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000 ======================================================== Clock O/P of MUXes DPLL PER H12 Output 192000000 CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204 DSI1_A_CLK : 136200000 DSI1_B_CLK : 0 DSI1_C_CLK : 136200000 DISPC_DIVISOR (0x58001804) = 0x00010001 2: LCD1 clk : 136200000 3: LCD2 clk : 192000000 10: LCD3 clk : 192000000 1: func clk : 192000000 LCD1 logic clk(/ 1 ) : 136200000 pix clk(/ 3 ) : 45400000 LCD2 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000 LCD3 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000
When dpi_out endpoint is given to tda19988_in, nothing works and the working dedicated hdmi also fails.
Can I get a detail on where to look.
Regards,
Padmesh