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Linux/DRA77P: Using LCD1 interface for HDMI in DRA77p

Part Number: DRA77P

Tool/software: Linux

Hi,

The previous thread has not been resolved, By mistake it was attended as resolved.

On running the debug clock scipt, I get the following, provided the device tree endpoint in dss tda19988_in is commented out.

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AB
video1 PLL :  Disabled
video2 PLL :  Disabled
HDMI   PLL :  Enabled
DSI1_A_CLK mux : DPLL HDMI
DSI1_B_CLK mux : DPLL video2
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00000000
 2: LCD1 clk switch :  DSS clk
 3: LCD2 clk switch :  DSS clk
10: LCD3 clk switch :  DSS clk
 1: func clk switch :  DSS clk
13: DPI1 output     :  HDMI

DSS_STATUS (0x5800005C) = 0x01408A81

DSI_CLK_CTRL (0x58004054) = 0x00000001

CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040B03

CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00000702

========================================================
Register dump for DPLL hdmi
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58040200    | 0x00000018 |
| 0x58040204    | 0x00000003 |
| 0x58040208    | 0x00000000 |
| 0x5804020C    | 0x0004A40E |
| 0x58040210    | 0x00602004 |
| 0x58040214    | 0x00001800 |
| 0x58040218    | 0x00000000 |
| 0x5804021C    | 0x00000000 |
| 0x58040220    | 0x00080000 |
|----------------------------|
Details for DPLL hdmi
PLL status  :  Locked
M4 hsdiv(1) :  inactive
M5 hsdiv(2) :  inactive
M6 hsdiv(3) :  inactive
M7 hsdiv(4) :  inactive

PLL_REGM   =  594
PLL_REGN   =  7
M4 DIV     =  0
M6 DIV     =  0
M7 DIV     =  0
PLL_REGM2  =  2
PLL_REGM_F =  2
PLL_SD  =  6
HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000
HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000

Clock calculations (DPLL hdmi)
sysclk = 20000000
CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000

========================================================
Clock O/P of MUXes
DPLL PER H12 Output 192000000
CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204

DSI1_A_CLK :  742500000
DSI1_B_CLK :  0
DSI1_C_CLK :  0

DISPC_DIVISOR (0x58001804) = 0x00010001

 2: LCD1 clk :  192000000
 3: LCD2 clk :  192000000
10: LCD3 clk :  192000000
 1: func clk :  192000000

LCD1 logic clk(/ 1 ) :  192000000  pix clk(/ 2 ) :  96000000
LCD2 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000
LCD3 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  4800000

When the dpi_out endpoint is made as lcd_out by giving a dummy lcd panel node, I get the following result,

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A2
video1 PLL :  Enabled
video2 PLL :  Disabled
HDMI   PLL :  Enabled
DSI1_A_CLK mux : DPLL Video1
DSI1_B_CLK mux : DPLL video2
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00010001
 2: LCD1 clk switch :  DSI1_A_CLK
 3: LCD2 clk switch :  DSS clk
10: LCD3 clk switch :  DSS clk
 1: func clk switch :  DSS clk
13: DPI1 output     :  LCD1

DSS_STATUS (0x5800005C) = 0x01408A82

DSI_CLK_CTRL (0x58004054) = 0x80004001

CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040F03

CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00001702

========================================================
Register dump for DPLL video1
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300    | 0x00000018 |
| 0x58004304    | 0x00002F83 |
| 0x58004308    | 0x00000000 |
| 0x5800430C    | 0x252AA44E |
| 0x58004310    | 0x02E56008 |
| 0x58004314    | 0x00000129 |
| 0x58004318    | 0x00000000 |
| 0x5800431C    | 0x00000000 |
| 0x58004320    | 0x00000000 |
|----------------------------|
Details for DPLL video1
PLL status  :  Locked
M4 hsdiv(1) :  Active
M5 hsdiv(2) :  Active
M6 hsdiv(3) :  Active
M7 hsdiv(4) :  Active

PLL_REGM   =  1362
PLL_REGN   =  39
M4 DIV     =  9
M6 DIV     =  9
M7 DIV     =  9

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1362000000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 136200000
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 136200000
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 136200000

========================================================
Register dump for DPLL hdmi
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58040200    | 0x00000018 |
| 0x58040204    | 0x00000003 |
| 0x58040208    | 0x00000000 |
| 0x5804020C    | 0x0004A40E |
| 0x58040210    | 0x00602004 |
| 0x58040214    | 0x00001800 |
| 0x58040218    | 0x00000000 |
| 0x5804021C    | 0x00000000 |
| 0x58040220    | 0x00080000 |
|----------------------------|
Details for DPLL hdmi
PLL status  :  Locked
M4 hsdiv(1) :  inactive
M5 hsdiv(2) :  inactive
M6 hsdiv(3) :  inactive
M7 hsdiv(4) :  inactive

PLL_REGM   =  594
PLL_REGN   =  7
M4 DIV     =  0
M6 DIV     =  0
M7 DIV     =  0
PLL_REGM2  =  2
PLL_REGM_F =  2
PLL_SD  =  6
HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000
HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000

Clock calculations (DPLL hdmi)
sysclk = 20000000
CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000

========================================================
Clock O/P of MUXes
DPLL PER H12 Output 192000000
CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204

DSI1_A_CLK :  136200000
DSI1_B_CLK :  0
DSI1_C_CLK :  136200000

DISPC_DIVISOR (0x58001804) = 0x00010001

 2: LCD1 clk :  136200000
 3: LCD2 clk :  192000000
10: LCD3 clk :  192000000
 1: func clk :  192000000

LCD1 logic clk(/ 1 ) :  136200000  pix clk(/ 3 ) :  45400000
LCD2 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000
LCD3 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000


When dpi_out endpoint is given to tda19988_in, nothing works and the working dedicated hdmi also fails.

Can I get a detail on where to look.

Regards,

Padmesh

  • Padmesh,

    By looking at the clock outputs, it looks like your HDMI is ruj=nning at 74.25 MHz. Is this expected.

    Also, when you add a dummy LCD, it is clocked at  45.4 MHz. What timings are you providing?

    It looks like when you are adding tda19988_in as dpi_out endpoint, one of the DT nodes that make the complete end-to-end connection is not enabled. Can you attach both the DTS files (with dummy LCD, and with the tda19988_in)?

    - Subhajit

  • Also, when you add tda19988_in as dpi_out endpoint, what does the DSS clock script show?

    Can you provide the output?

  • Hi Subhajit,

    I have provided just a sample frequency for dummy lcd. For HDMI, I have not done any changes to the clock.

    I have attached the following DTs.

    /*
     * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    #include "dra76-evm.dts"
    
    / {
    	aliases {
    		display0 = &hdmi1;
    		display1 = &hdmi0;
    	};
    	
    	
    
    
    	hdmi1: connector@0 {
    		compatible = "hdmi-connector";
    		label = "hdmilcd";
    
    		digital;
    
    		ddc-i2c-bus = <&i2c3>;
    
    		hpd-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;	/* wakeup2/sys_nirq2/gpio1_2 HPD */
    
    		port {
    			hdmi1_connector_in: endpoint {
    				remote-endpoint = <&tda19988_out>;
    			};
    		};
    	};
    };
    
    &dss {
    	status = "ok";
    	ports {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		status = "ok";
    
    		port {
    			reg = <0>;
    
    			dpi_out: endpoint {
    				remote-endpoint = <&tda19988_in>;
    				data-lines = <24>;
    			};
    		};
    	};
    };
    
    
    &epwmss0{
    	
    	status = "okay";
    };
    
    &ehrpwm0{
    
    	status = "okay";
    
    };
    
    &ecap0{
    	
    	status = "okay";
    	
    };
    
    &i2c3 {
    	clock-frequency = <100000>;
    
    	tda19988: tda19988@70 {
    		compatible = "nxp,tda998x";
    		reg = <0x70>;
    		
    		video-ports = <0x230145>;
    
    		ports {
    			port@0 {
    				tda19988_in: endpoint@0 {
    					remote-endpoint = <&lcd_out>;
    					lanes = <0 1 2 3 4 5 6 7 8 9>;
    				};
    			
    			};
    			port@1 {
    				tda19988_out: endpoint@1{
    					remote-endpoint = <&hdmi1_connector_in>;
    				};
    			};
    		};
    	};
    
    };
    

    /*
     * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    #include "dra76-evm.dts"
    
    / {
    
    	aliases {
    		display0 = &lcd;
    		display1 = &hdmi0;
    	};
    		
    		
    	lcd: display {
    		/*
    		 * TODO: Not a DPI panel, but a dummy DSI video mode panel.
    		 * This needs to be changed later when we can support DSI VM
    		 * panels properly.
    		 */
    		compatible = "osd,osd101t2045-53ts", "panel-dpi";
    
    		label = "lcd";
    
    		panel-timing {
    			clock-frequency = <45400000>;
    			hactive = <1920>;
    			vactive = <1200>;
    
    			hfront-porch = <112>;
    			hback-porch = <32>;
    			hsync-len = <16>;
    
    			vfront-porch = <16>;
    			vback-porch = <16>;
    			vsync-len = <2>;
    
    			hsync-active = <0>;
    			vsync-active = <0>;
    			de-active = <1>;
    			pixelclk-active = <1>;
    		};
    
    				
    		ports{	
    			port@0 {
    				lcd_in: endpoint {
    					remote-endpoint = <&dpi_out>;
    				};
    			};
    
    		};
    
    	};
    
    
    };
    
    &dss {
    	status = "ok";
    	ports {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		status = "ok";
    
    		port {
    			reg = <0>;
    
    			dpi_out: endpoint {
    				remote-endpoint = <&lcd_in>;
    				data-lines = <24>;
    			};
    		};
    	};
    };
    
    
    &epwmss0{
    	
    	status = "okay";
    };
    
    &ehrpwm0{
    
    	status = "okay";
    
    };
    
    &ecap0{
    	
    	status = "okay";
    	
    };
    
    &i2c3 {
    	clock-frequency = <100000>;
    
    	pcf_tfp: pcf8757@20 {
    		compatible = "ti,pcf8575", "nxp,pcf8575";
    		reg = <0x27>;
    		gpio-controller;
    		#gpio-cells = <2>;
    
    		p2 {
    			gpio-hog;
    			gpios = <2 GPIO_ACTIVE_HIGH>;
    			output-high;
    			line-name = "ct_hpd";
    		};
    
    		p3 {
    			gpio-hog;
    			gpios = <3 GPIO_ACTIVE_HIGH>;
    			output-high;
    			line-name = "ls_oe";
    		};
    	};
    	
    };
    

    Regards,

    Padmesh

  • When I add tda19988_in as the dpi_out endpoint, the DSS clock script shows,

    =====================DSS clock script===================
    Dumps internal clocks and muxes of DSS
    
    CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AF
    video1 PLL :  Disabled
    video2 PLL :  Disabled
    HDMI   PLL :  Disabled
    DSI1_A_CLK mux : DPLL HDMI
    DSI1_B_CLK mux : DPLL video2
    DSI1_C_CLK mux : DPLL Video1
    
    DSS_CTRL (0x58000040) = 0x
    
    !!! OUPS... MEMORY ERROR @ 0x00000000 !!!
    Are you sure that:
        MEMORY ADDRESS IS VALID?
        TARGETED MODULE IS CLOCKED?
     2: LCD1 clk switch : 
     3: LCD2 clk switch : 
    10: LCD3 clk switch : 
     1: func clk switch : 
    13: DPI1 output     : 
    
    DSS_STATUS (0x5800005C) = 0x
    
    !!! OUPS... MEMORY ERROR @ 0x00000000 !!!
    Are you sure that:
        MEMORY ADDRESS IS VALID?
        TARGETED MODULE IS CLOCKED?
    
    DSI_CLK_CTRL (0x58004054) = 0x00000000
    
    CM_DSS_CLKSTCTRL (0x4A009100) = 0x00000003
    
    CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00070000
    
    ========================================================
    Clock O/P of MUXes
    DPLL PER H12 Output 192000000
    CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000004
    
    DSI1_A_CLK :  0
    DSI1_B_CLK :  0
    DSI1_C_CLK :  0
    
    DISPC_DIVISOR (0x58001804) = 0x
    
    !!! OUPS... MEMORY ERROR @ 0x00000000 !!!
    Are you sure that:
        MEMORY ADDRESS IS VALID?
        TARGETED MODULE IS CLOCKED?
    
     2: LCD1 clk : 
     3: LCD2 clk : 
    10: LCD3 clk : 
     1: func clk : 
    
    LCD1 logic clk(/ ) :  0  pix clk(/ ) :  0
    LCD2 logic clk(/ ) :  0  pix clk(/ ) :  0
    LCD3 logic clk(/ ) :  0  pix clk(/ ) :  0
    

    The working HDMI fails here.

  • Ok, the DSS clock script says that the video / hdmi PLLs are not even turned on.

    I can see that you have provided 45.4 MHz as dummy LCD clock, that clears the confusion.

    Can you provide the output of "modetest" when you can boot using only HDMI? That will help me understand where the 74.25 MHz is coming from. My hunch is 1920x1080@30, but I would still like to confirm

  • Using only HDMI, modetest shows the following

    trying to open device 'i915'...failed
    trying to open device 'amdgpu'...failed
    trying to open device 'radeon'...failed
    trying to open device 'nouveau'...failed
    trying to open device 'vmwgfx'...failed
    trying to open device 'omapdrm'...done
    Encoders:
    id	crtc	type	possible crtcs	possible clones	
    34	39	TMDS	0x00000001	0x00000000
    
    Connectors:
    id	encoder	status		name		size (mm)	modes	encoders
    35	34	connected	HDMI-A-1       	700x390		31	34
      modes:
    	name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
      1280x720 60 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: preferred, driver
      1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
      1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 148352 flags: phsync, pvsync; type: driver
      1920x1080i 60 1920 2008 2052 2200 1080 1084 1094 1125 74250 flags: phsync, pvsync, interlace; type: driver
      1920x1080i 60 1920 2008 2052 2200 1080 1084 1094 1125 74176 flags: phsync, pvsync, interlace; type: driver
      1920x1080 50 1920 2448 2492 2640 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
      1920x1080i 50 1920 2448 2492 2640 1080 1084 1094 1125 74250 flags: phsync, pvsync, interlace; type: driver
      1280x1024 75 1280 1296 1440 1688 1024 1025 1028 1066 135000 flags: phsync, pvsync; type: driver
      1440x900 85 1440 1544 1696 1952 900 903 909 948 157000 flags: nhsync, pvsync; type: driver
      1440x900 75 1440 1536 1688 1936 900 903 909 942 136750 flags: nhsync, pvsync; type: driver
      1440x900 60 1440 1488 1520 1600 900 903 909 926 88750 flags: phsync, nvsync; type: driver
      1280x720 60 1280 1390 1430 1650 720 725 730 750 74176 flags: phsync, pvsync; type: driver
      1280x720 50 1280 1720 1760 1980 720 725 730 750 74250 flags: phsync, pvsync; type: driver
      1024x768 75 1024 1040 1136 1312 768 769 772 800 78750 flags: phsync, pvsync; type: driver
      1024x768 70 1024 1048 1184 1328 768 771 777 806 75000 flags: nhsync, nvsync; type: driver
      1024x768 60 1024 1048 1184 1344 768 771 777 806 65000 flags: nhsync, nvsync; type: driver
      800x600 75 800 816 896 1056 600 601 604 625 49500 flags: phsync, pvsync; type: driver
      800x600 72 800 856 976 1040 600 637 643 666 50000 flags: phsync, pvsync; type: driver
      800x600 60 800 840 968 1056 600 601 605 628 40000 flags: phsync, pvsync; type: driver
      800x600 56 800 824 896 1024 600 601 603 625 36000 flags: phsync, pvsync; type: driver
      720x576 50 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type: driver
      720x576i 50 720 732 795 864 576 580 586 625 13500 flags: nhsync, nvsync, interlace, dblclk; type: driver
      720x480 60 720 736 798 858 480 489 495 525 27027 flags: nhsync, nvsync; type: driver
      720x480 60 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driver
      720x480i 60 720 739 801 858 480 488 494 525 13514 flags: nhsync, nvsync, interlace, dblclk; type: driver
      720x480i 60 720 739 801 858 480 488 494 525 13500 flags: nhsync, nvsync, interlace, dblclk; type: driver
      640x480 75 640 656 720 840 480 481 484 500 31500 flags: nhsync, nvsync; type: driver
      640x480 73 640 664 704 832 480 489 492 520 31500 flags: nhsync, nvsync; type: driver
      640x480 60 640 656 752 800 480 490 492 525 25200 flags: nhsync, nvsync; type: driver
      640x480 60 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type: driver
      720x400 70 720 738 846 900 400 412 414 449 28320 flags: nhsync, pvsync; type: driver
      props:
    	1 EDID:
    		flags: immutable blob
    		blobs:
    
    		value:
    			00ffffffffffff003190544c01000000
    			01140103814627788aa58ea6544a9c26
    			124546afcf009500950f951901010101
    			010101010101011d007251d01e206e28
    			5500b9882100001e8c0ad08a20e02d10
    			103e9600b98821000018000000fd0032
    			4b183c0b000a202020202020000000fc
    			0033325633482d4836410a2020200145
    			020321714e0607020315961112130414
    			051f90230907078301000065030c0010
    			008c0ad090204031200c405500b98821
    			000018011d8018711c1620582c2500b9
    			882100009e011d80d0721c1620102c25
    			80b9882100009e011d00bc52d01e20b8
    			285540b9882100001e023a80d072382d
    			40102c4580b9882100001e00000000d0
    	2 DPMS:
    		flags: enum
    		enums: On=0 Standby=1 Suspend=2 Off=3
    		value: 0
    	5 link-status:
    		flags: enum
    		enums: Good=0 Bad=1
    		value: 0
    
    CRTCs:
    id	fb	pos	size
    39	55	(0,0)	(1280x720)
      1280x720 60 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: preferred, driver
      props:
    	23 CTM:
    		flags: blob
    		blobs:
    
    		value:
    	24 GAMMA_LUT:
    		flags: blob
    		blobs:
    
    		value:
    	25 GAMMA_LUT_SIZE:
    		flags: immutable range
    		values: 0 4294967295
    		value: 256
    	30 background:
    		flags: range
    		values: 0 16777215
    		value: 0
    	31 trans-key-mode:
    		flags: enum
    		enums: disable=0 gfx-dst=1 vid-src=2
    		value: 0
    	32 trans-key:
    		flags: range
    		values: 0 16777215
    		value: 0
    	33 alpha_blender:
    		flags: range
    		values: 0 1
    		value: 0
    	37 rotation:
    		flags: bitmask
    		values: rotate-0=0x1 rotate-90=0x2 rotate-180=0x4 rotate-270=0x8 reflect-x=0x10 reflect-y=0x20
    		value: 1
    	27 zorder:
    		flags: range
    		values: 0 3
    		value: 0
    
    Planes:
    id	crtc	fb	CRTC x,y	x,y	gamma size	possible crtcs
    36	39	55	0,0		0,0	0       	0x00000001
      formats: RX12 AR12 RG16 XR24 RG24 AR24 RA24 RX24 AR15 XR12 RA12 XR15
      props:
    	6 type:
    		flags: immutable enum
    		enums: Overlay=0 Primary=1 Cursor=2
    		value: 1
    	37 rotation:
    		flags: bitmask
    		values: rotate-0=0x1 rotate-90=0x2 rotate-180=0x4 rotate-270=0x8 reflect-x=0x10 reflect-y=0x20
    		value: 1
    	27 zorder:
    		flags: range
    		values: 0 3
    		value: 0
    	38 zpos:
    		flags: range
    		values: 0 3
    		value: 0
    	28 global_alpha:
    		flags: range
    		values: 0 255
    		value: 255
    	29 pre_mult_alpha:
    		flags: range
    		values: 0 1
    		value: 0
    40	0	0	0,0		0,0	0       	0x00000001
      formats: RG16 RX12 YUYV AR15 RA24 NV12 RA12 XR24 RG24 UYVY AR12 XR15 AR24 XR12 RX24
      props:
    	6 type:
    		flags: immutable enum
    		enums: Overlay=0 Primary=1 Cursor=2
    		value: 0
    	41 rotation:
    		flags: bitmask
    		values: rotate-0=0x1 rotate-90=0x2 rotate-180=0x4 rotate-270=0x8 reflect-x=0x10 reflect-y=0x20
    		value: 1
    	27 zorder:
    		flags: range
    		values: 0 3
    		value: 1
    	42 zpos:
    		flags: range
    		values: 0 3
    		value: 1
    	28 global_alpha:
    		flags: range
    		values: 0 255
    		value: 255
    	29 pre_mult_alpha:
    		flags: range
    		values: 0 1
    		value: 0
    45	0	0	0,0		0,0	0       	0x00000001
      formats: RG16 RX12 YUYV AR15 RA24 NV12 RA12 XR24 RG24 UYVY AR12 XR15 AR24 XR12 RX24
      props:
    	6 type:
    		flags: immutable enum
    		enums: Overlay=0 Primary=1 Cursor=2
    		value: 0
    	46 rotation:
    		flags: bitmask
    		values: rotate-0=0x1 rotate-90=0x2 rotate-180=0x4 rotate-270=0x8 reflect-x=0x10 reflect-y=0x20
    		value: 1
    	27 zorder:
    		flags: range
    		values: 0 3
    		value: 2
    	47 zpos:
    		flags: range
    		values: 0 3
    		value: 2
    	28 global_alpha:
    		flags: range
    		values: 0 255
    		value: 255
    	29 pre_mult_alpha:
    		flags: range
    		values: 0 1
    		value: 0
    50	0	0	0,0		0,0	0       	0x00000001
      formats: RG16 RX12 YUYV AR15 RA24 NV12 RA12 XR24 RG24 UYVY AR12 XR15 AR24 XR12 RX24
      props:
    	6 type:
    		flags: immutable enum
    		enums: Overlay=0 Primary=1 Cursor=2
    		value: 0
    	51 rotation:
    		flags: bitmask
    		values: rotate-0=0x1 rotate-90=0x2 rotate-180=0x4 rotate-270=0x8 reflect-x=0x10 reflect-y=0x20
    		value: 1
    	27 zorder:
    		flags: range
    		values: 0 3
    		value: 3
    	52 zpos:
    		flags: range
    		values: 0 3
    		value: 3
    	28 global_alpha:
    		flags: range
    		values: 0 255
    		value: 255
    	29 pre_mult_alpha:
    		flags: range
    		values: 0 1
    		value: 0
    
    Frame buffers:
    id	size	pitch

  • In the DTS file dra76-evm-with_tda19988_as_endpoint.txt:


    tda19988: tda19988@70 {
    compatible = "nxp,tda998x";
    reg = <0x70>;

    video-ports = <0x230145>;

    ports {
    port@0 {
    tda19988_in: endpoint@0 {
    remote-endpoint = <&lcd_out>;
    lanes = <0 1 2 3 4 5 6 7 8 9>;
    };

    Shouldn't remote-endpoint be dpi_out? Can you try that?

    Also do you have a driver that understands compatible = "nxp,tda998x"? Does a driver probe happen?

    - Subhajit

  • I changed it to dpi_out, but still the same issue.

    Yes the driver is probed, as i can see the i2c device

    root@dra7xx-evm:~# cat /sys/class/i2c-dev/i2c-2/device/2-0070/modalias 
    i2c:tda998x
    

  • Padmesh,

    This is the device node. To confirm that the driver is successfully probed and is operational, find the source code and put some printk statements to see if the probe happened.

    Also , please send me the output of "dmesg | grep -i drm" and "dmesg | grep -i dss"

  • Ok I'll check that.

    Output of dmesg | grep -i drm with tda19988_in endpoint removed

    [    0.000000] Kernel command line: console= elevator=noop root=PARTUUID=760e384e-02 rw rootwait fixrtc loglevel=0 omapdrm.num_crtc=2 consoleblank=0 cma=128M@0xB0000000 rootfstype=ext4 snd.slots_reserved=1,1
    [    3.145884] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
    [    3.145889] [drm] No driver support for vblank timestamp query.
    [    3.418767] [drm] Enabling DMM ywrap scrolling
    [    3.448657] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
    [    3.449266] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
    [    7.094600] [drm] Initialized pvr 1.14.3699939 20110701 for 56000000.gpu on minor 1
    

    And output of dmesg | grep -i dss

    [    2.813818] DSS: OMAP DSS rev 6.1
    [    2.815651] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
    [    2.816278] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
    

  • I actually wanted this logs with the tda19988_in endpoint. Can you provide?

  • With  tda19988 endpoint

    [    6.829501] [drm] Initialized pvr 1.14.3699939 20110701 for 56000000.gpu on minor 0
    

    [    2.796926] DSS: OMAP DSS rev 6.1
    [    2.798770] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
    [    2.799394] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
    

  • It looks like the DRM driver omapdrm is not getting probed. My hunch is it is getting -EPROBE_DEFER error.

    Can you confirm? You can add printk statements in all return paths in dev_load in omap_drv.c

    Do not use initcall_debug as EPROBE_DEFERs are considered as success in initcall_debug path

  • I cannot find dev_load in omap_drv.c

  • Is this kernel 4.4? I can see a dev_load function in omap_drv.c:721

    You can trace this function as well as pdev_probe() in the same file.

    One of them must be returning an error.

    Let me know 

  • We are using kernel version 4.14

  • Ok, in that case all the functionalities of dev_load are inside pdev_probe. Kindly trace pdev_probe and see why the function is returning with an error.

    - Subhajit

  • Hi Subhajit,

    On making the DRM as modules in kernel and with tda19988_in as endpoint on probing tda998x driver, the following is happening

    root@dra7xx-evm:~# dmesg | grep -i drm_message
    [   12.941237] ****************drm_message: Inside pdev_probe ****************
    [   12.941274] ****************drm_message: platform_set_drvdata(pdev, ddev) is called****************
    [   12.941278] ****************drm_message: omap_crtc_pre_init() is called****************
    [   12.941282] ****************drm_message: goto err_crtc_uninit****************
    root@dra7xx-evm:~# modprobe tda998x
    [   87.014228] ****************drm_message: Inside pdev_probe ****************
    root@dra7xx-evm:~# [   87.021827] ****************drm_message: platform_set_drvdata(pdev, ddev) is called****************
    [   87.032249] ****************drm_message: omap_crtc_pre_init() is called****************
    [   87.040378] ****************drm_message: goto err_crtc_uninit****************
    [   87.047984] connector-hdmi connector@0: failed to find video source
    

    I find that they are going to err_crtc_uninit

    Inside the omap_connect_dssdev(), -EPROBE_DEFER is returned at  if (!omap_dss_stack_is_ready())

  • Hi Subhajit,

    We have found that it comes when omap_dss_stack_is_ready() which returns a false value. What issue might it indicate ?

  • omap_dss_stack_is_ready returns false / error when one of the components in teh entire chain is not probed correctly.

    In my opinion the tda19988 is not getting probed.

    Can you verify (by putting some prints) that  the tda19988 is probed successfully?

  • Hi Subhajit,

    Trying to insert tda998x driver shows the following messages from omap_drv.c, No prints from tda998x is shown

    [  105.436159] ****************drm_message: Inside pdev_probe ****************
    [  105.436269] ****************drm_message: platform_set_drvdata(pdev, ddev) is called****************
    [  105.436275] ****************drm_message: omap_crtc_pre_init() is called****************
    [  105.436285] ****************drm_message: omapdss_stack_is_ready() is false****************
    [  105.436290] ****************drm_message: goto err_crtc_uninit****************
    [  105.436296] ****************drm_message: omap_crtc_pre_uninit() is called****************
    [  105.436329] ****************drm_message: drm_dev_unref(ddev) is called****************
    [  105.436672] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector@0[0]'
    [  105.436733] connector-hdmi connector@0: failed to find video source
    

  • Can you find out why parsing "hpd-gpios" is failing? Is it some IO expander?

    Also, put some prints in the tda19988 driver to see if the probe passed

  • Hi Subhajit,

    I have provided prints in tda998x driver but nothing is shown. The above printk messages (from omap_drv.c ) occur in the kernel log every time on inserting the tda998x driver.

    I believe hpd_gpios usage is not necessary in the device tree.

  • As discussed over call, I am closing this