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Original question:

TMS320C6678: PCIE root complex problem - there is link, can access to PCIE configuration space, but cannot access to the...

CCS/TMS320C6678: PCIE root complex problem - there is link, can access to PCIE configuration space, access to bar0 but cannot access to the bar1 memory in the End point

Zvi Marks
Prodigy 70 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hi,

In continue of my question  https://e2e.ti.com/support/processors/f/791/t/822540, I have another issue.

When the I configured the fpga bar size to 128MB, I can access only to the bar0 and I can not access to bar1.

And when I configured the fpga bar size to 1MB, I can access to the both bars.

Am I loss something?

Thanks,

Zvi

  • 0
    TI__Guru**** 161600 points

    Hi,

    These modifications are done on FPGA side as I understand, am I correct? If so, then you should consult the FPGA vendor.

    Best Regards,
    Yordan

  • 0
    Guru 13202 points

    Hi!

    Would be nice to know a little more details about your setup and how do you make accesses, is that PIO access to memory mapped part or that should be DMA.

    Nevertheless, as you had success with 1MB apertures, the answer is likely between base addresses and address translations. Please provide more details so we could take a look. Meanwhile you may try to play with BAR sizes as 1, 2, 4, 8 MB to see which one works and which one fails.

  • 0 in reply to Victor Kazmirenko
    Prodigy 70 points

    Hi,

    Sorry on the delay. we are using with "out bound" via direct DSP configurations and the "in bound" by dma on the FPGA side(called discriptor bypass mode).

    My bars region is 128 MB  for each bar, total 2 bars.

    For now, the system is worked. the solutions are that not address translation on the FPGA, need  to configure the bar address need to 0x0 in the out bound(in the FPGA side) and on the in bound (in the DSP side).

    Thanks, 

    Zvi Marks