TMS320C6746: MPU test

Hi Nancy,

Is cache enabled? I wonder if it's writing to cache instead. Can you try with cache disabled by disabling the MAR bits for that DDR region?

This can be done in the .cfg file, for example;

var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');

/* Set 0xc0000000 -> 0xc3ffffff to be non-cached.
 * Set 0xc4000000 -> 0xc4ffffff to be cached.
 */
Cache.MAR192_223 = 0x00000010;

The MARs are defined in Table 4-21 in the TMS320C674x DSP Megamodule Reference Guide.

Regards,
Sahin

Hi Nancy,

Any update on this?

Regards,
Sahin

Hi,

The customer just test the demo, so he didn't enable cache. He has checked registers and they are configured successfully.

Hi Nancy,

Could the customer provide a register dump for the MPPA register? And has the customer done memory testing on their custom board to ensure that DDR connectivity is reliable?

Hi,

Sorry for the wrong information. The customer seems opened cache.

Hi Nancy,

Does the customer still need assistance with this issue?