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Original question:

AM3352: Cache invalidate procedure

TMS320C6678: DMA is moving blank data from cached ddr

Richard Breyer
Intellectual 430 points

Part Number: TMS320C6678

This problem is a c66 corepac problem occurring on a c6678:

I am moving data via dma from ddr to l2. When this data is dmaed from the msmc everything works, but the dma from the DDR move always shoots blanks.

I suspect that the cache is involved in this problem. (According to the code composer memory browser the DDR data I am trying to move is in L1 and L2 data caches at dma time.)

The data that appears at the dst is all 0s even if some other data was written there. In other words, the data which is theoretically located in the DDR never finds its way to its intended destination, instead the destination location is blanked, although the dma definitely executes and even correctly links to another dma and fires an interrupt. That is why I figure that cache is involved although its operation is so shrouded in hardware that probative evidence is hard to come by.

Is there some way to make sections of the DDR off limits to the cache engine, so I can rule tis out? I can easily map the stuff I need into forbidden locations if there is some way I can protect these DDR locations from the cache.

  • 0
    TI__Guru* 95265 points

    Hi,

    The easiest way to try this is to put DDR non-cached. This is controlled by MAR128 to MAR 255 in the http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf, see table 4-20 Memory Attribute Registers. Each MAR controls 16MB DDR.

    You can simply use *(unsigned int*)0x184_8200 = 0xC to turn the first 16MB DDR cache off. Then you should see that what inside DDR moved to L2 by EDMA.

    In the real world, the DDR cache is turned on for performance. This caused the cache coherency issue between what CPU see and DMA see. The cache coherency is not maintained by DSP hardware, it is your software's job. When L2 and DDR cache turned on, CPU always see the cache's data, however the EDMA always use the real physical memory data.

    Let's say, you use CPU to write a pattern into DDR, the data is in cache actually, you must do a cache invalidate and write back to make the data lands on the DDR. Then you use EDMA to move data to L2. It is in L2, but CPU only see the cached L2 data, not what you really received. You need to do a cache invalidate to throw away what inside L2 cache, so the CPU will read from L2 and see your new data moved by EDMA.

    Regards, Eric