What are the minimum setup and hold-times for SYSBOOT[15:0] to PWRONRSTn rising edge?
Our design uses a logic multiplexer IC to switch the SYSBOOT pin connections based on the state of PWRONRSTn. When the PWRONRSTn transitions from low to high, the multiplexer switches the pins to their LCD_DATA[] functions on the PCB. We need to know how long the SYSBOOT pin states must be held after the rising edge of PWRONRSTn. This should be a characterized timing like all the other hold-time specs.
The question was asked in the past but was not answered correctly: https://e2e.ti.com/support/processors/f/791/t/324739
Thanks
