Hi,
I experience issues with the SPI master in the AM5728.
It looks it is related to the case in https://e2e.ti.com/support/processors/f/791/t/767438 which is set to solved although there is no solution.
It is our own board and I see different behavior on different boards. Some boards work partially or fine.
It is using Linux and the configuration is based on SDK.05.03
As some boards work I assume the software configuration is correct.
What I see is that the bits are clocked out correctly from the AM5728, the spi slave device is responding correctly to the command send but the data received in AM5728 McSPI is incorrect. In some cases it looks like every bit is received twice.
To me it looks like there are signal reflections on the spi clock line which is causing that bits are clocked in multiple times (although not seen on the scope measured at the spi slave device).
I know the board layout has some mistakes on the spi lines like there is no series resistor on the spi clock.
When I look at the block diagram of the McSpi (figure 24-83 of the AM572x TRM spruhz6j.pdf) it looks like the Spi master is generating the spi clock but this clock is read back from the io pin to clock in the data.
This means that if there are reflections on the line it can happen that the spi controller can see multiple clock edges and clock in bits multiple times.
- Is the hypothesis described above correct about how the spi clock works and can reflections causing this behavior?
- Is there a possibility to change the configuration of the io pin or the McSPI controller to prevent the issues? The only thing I could find was changing the slew-rate. This helps a little bit but doesn't solve it.
regards, Robert
