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Original question:

TMS320C5517: McSPI usage

TMS320C5517: McSPI usage 2

Kz777
Expert 7895 points

Part Number: TMS320C5517

Hi Champs,

Based on previous answer, 

We have additional question from customer

1: EOT bit timing method.

They understand clock skip is able to detect EOT function.

However, we don't know this detail setting.

So, do you have any interrupt that synchronize to EOT bit changing ?

Or we would like to know such a information 

"When xxx interrupt happen, EOT bit will be "1" (complete transmit) in xxx sec "

Or Could you please tell us any recommend to use EOT bit (error detection method) ? 

2. How to reset bit count on the McSPI CS Active

   Currently, customer is using the most simple slave setting that is not using a FIFO and DMA

  At this environment , we have never seen bit count reset phenomenon that is commented by TI comment.

 So, Could you please tell us bit coun reset method in case of not using FIFO and DMA at slave ?

Regards,

Kz777

  • 0
    TI__Expert 7895 points

    Hi Champs,

    Could you please provide us any comment ?

  • 0 in reply to Kz777
    TI__Expert 7895 points

    Hi Champs,

    Could you please provide any comment ?

  • 0 in reply to Kz777
    TI__Mastermind 30280 points

    Hi Kaz-san,

    Sorry, I am frustrated by the McSPI lack of support for error reporting.

    There appears to be no interrupt tied to the EOT bit. Perhaps the software can poll the EOT bit, or implement a timeout and then check the EOT bit. This assumes that the EOT bit does change state when the unexpected CS deassertion occurs in the middle of receiving a word.

    Kz777 said:
    At this environment , we have never seen bit count reset phenomenon that is commented by TI comment.



    What counter are you referring to? I don't think you have visibility to the bit count through any register. There is only word counter from what I can see.

    Wishing I could be more helpful,
    Mark

  • 0 in reply to Mark M
    TI__Prodigy 500 points

    Hello Mark,

    Thanks for your comment and we have further questions need to be solved here.

    1. EOT bit timing method.

    Customer does not understand what the factor is to judge time out.

    What kind of factor should we monitor time out at trigger?

    Furthermore, how long if EOT does not change, we can decide judge that it is time out?

    2. How to reset bit count on the McSPI CS Active

       Customer does not mean they are going to monitor specific register.

    To be specific, they can confirm the following function of McSPI

    • Safe mode in C5517 McSPI
      • Set SPI word length (WL bit) = 0x7 (8BIT) and send fixed date(e.g : 0xFB)
    • Intentionally change the numbers of CLK during CS="L" at master device side
      • (e.g : Usually send CLK for 8 times, but send 9 times)
    • When we monitor the output data from McSPI_SOMI at C5517, the fixed data should be sending. 
      • There is 1 bit shifting difference for each 1 word at the output data

     If we can reset bit count at the timing of CS="H"or CS="L" next time, fixed data(0xFB) should be always sent.

    So, Could you please tell us bit count reset method in case of not using FIFO and DMA at slave ?

    thank you.

    HsinYu Lin

  • 0 in reply to user5237784
    TI__Mastermind 30280 points

    Hi Lin-san,

    I do not know why the EOT bit is not getting set. Below I have added information from the McSPI spec document to the information from the TRM:

    CH0STATL register bit 2 EOT
    0x0 = (TRM) Shift register is loaded with the data from the transmitter register
              (Spec) bit is cleared when the shift register is loaded with the data from the transmitter register - beginning of transfer
    0x1 = (TRM) End of an SPI transfer
              (Spec) bit is automatically set to one at the end of an SPI transfer
          
    One sure way to clear the bit counter is to reset the peripheral with the soft reset bit:

    SYSCONFIGL register bit 1 SOFTRESET can be used to reset the McSPI peripheral to default state. The McSPI peripheral must be reinitialized before use.

    A timer interrupt (or RTC interrupt) could be used as a timeout for McSPI. If the timer interrupt service routine detects that no McSPI data has been received in a long time (multiple missed words), then it can be used to recover the McSPI peripheral with a soft reset or a peripheral reset operation.

    Regards,
    Mark