Hello
I clicked "resolved" button by mistake on previos question.
- LINK : http://e2e.ti.com/support/processors/f/791/t/837816
I attated summarized DRU and UDMA throughput again.
I recieved a message from Sivaraj
I'm sorry, I can't understand the first answer exactly. The second answer is OK.
From what I understand about the 1st answer :
- UDMA and DUR can do 1 task on 1 channel. (If they do 2 tasks, it needs 2 channel.)
- In other words, If DMAs(UDMA, DRU) use 2 channel, there are 2 tasks.
- In the 1st answer, cache is loated in MSMC. I attached MSMC block diagram(Figure 8-3 in TRM) as well.
- If DRU does "a" task to transfer 1MB from/to DDR, datapath would be DDR(Read) -> cache(in MSMC) -> DDR(Write).
- But If DRU does "b" task to transfer 2MB from/to DDR before "a" task is completed, cache miss will occur in "a" task.
- DMA will read again to store on cache and then write to DDR. An interrupt will occur at that time as well.
- Hence, DRU transfer using multi channel is not efficiency and CPU loas could be high because of a lot of interrupts.
Could you please check above thinsg that I've understood ?
And It's really helpful for me to expain more details.
Best regards
Yongsig.