AM5708: CSI2 PHY setup problem

Andrei Kolganov

Part Number: AM5708
Other Parts Discussed in Thread: DM385

Hi,

I need to start CAMSS module of AM5708 under RTOS. I took as a base of Linux driver for CSI2_PHY. I can't understand what I should do flag RESET_DONE set in register CAL_CSI2_COMPLEXIO_CFG_0 .

For the first I configure module CSI2_PHY

//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

HW_WR_REG32(0x4845B330, 0x00000001); // CAL_CSI2_CTX0_0
// DT DT type: MIPI CSI-2 Specs
// 0x1: All - DT filter is disabled
// 0x24: RGB888 1 pixel = 3 bytes
// 0x2B: RAW10 4 pixels = 5 bytes
// 0x2A: RAW8 1 pixel = 1 byte
// 0x1E: YUV422 2 pixels = 4 bytes
// VC (Virtual Channel) is 0
// NUM_LINES_PER_FRAME => 0 means auto detect

HW_WR_REG32(0x4845B304, 0x00000123); // CAL_CSI2_COMPLEXIO_CFG_0
// Clock - pos 3
// Data[0] - pos 2
// Data[1] - pos 1

// Enable IRQ_WDMA_END 0 / 1
HW_WR_REG32(0x4845B028 + 0x10, 0x00000001); // CAL_HL_IRQENABLE_SET_1
// Enable IRQ_WDMA_START 0 / 1
HW_WR_REG32(0x4845B028 + 0x20, 0x00000001); // CAL_HL_IRQENABLE_SET_1
// Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling
HW_WR_REG32(0x4845B318, 0xFF000000); // CAL_CSI2_VC_IRQENABLE_0

/* Steps

* 1. Configure D-PHY mode and enable required lanes
* 2. Reset complex IO - Wait for completion of reset
* Note if the external sensor is not sending byte clock,
* the reset will timeout
* 3 Program Stop States
* A. Program THS_TERM, THS_SETTLE, etc... Timings parameters
* in terms of DDR clock periods
* B. Enable stop state transition timeouts
* 4.Force FORCERXMODE
* D. Enable pull down using pad control
* E. Power up PHY
* F. Wait for power up completion
* G. Wait for all enabled lane to reach stop state
* H. Disable pull down using pad control
*/

/* 1. Configure D-PHY mode and enable required lanes */
HW_WR_REG32(0x4A002E94, 0x00026400); // CTRL_CORE_CAMERRX_CONTROL
// CSI_CTRLCLKEN = 1
// CSI0_CAMMODE = 0 (DPHY mode)
// CSI0_LANEENABLE = 3 (2 lanes enable)
// CSI0_MODE = 1
UARTConfigPrintf(DEBUG_UART_BASE, "CTRL_CORE_CAMERRX_CONTROL(0x4A002E94): %08X\n", HW_RD_REG32(0x4A002E94));

/* 2. Reset complex IO - Do not wait for reset completion */
dwTmp = HW_RD_REG32(0x4845B304);
HW_WR_REG32(0x4845B304, dwTmp | 0x40000000); // CAL_CSI2_COMPLEXIO_CFG_0
// RESET_CTRL = 1 (Complex IO reset de-asserted)
dwTmp = HW_RD_REG32(0x4845B304); // Dummy read to allow SCP to complete
UARTConfigPrintf(DEBUG_UART_BASE, "CAL_CSI2_COMPLEXIO_CFG_0(0x4845B304): %08X\n", dwTmp);

/* 3.A. Program Phy Timing Parameters */
//UARTConfigPrintf(DEBUG_UART_BASE, "REG0(0x4845B800): %08X\n", HW_RD_REG32(0x4845B800));
HW_WR_REG32(0x4845B800, 0x01000427); // THS_SETTLE = 0x27 (for 400 MHz) Programmed value = floor(105 ns/DDRClk period) + 4
// THS_TERM = 0x04 (for 400 MHz) Programmed value = floor(20 ns/DDRClk period)
// HSCLOCKCONFIG = 1 (Disable clock missing detector)
UARTConfigPrintf(DEBUG_UART_BASE, "REG0(0x4845B800): %08X\n", HW_RD_REG32(0x4845B800));

//UARTConfigPrintf(DEBUG_UART_BASE, "REG1(0x4845B804): %08X\n", HW_RD_REG32(0x4845B804));
HW_WR_REG32(0x4845B804, 0x0002E10E); // Default Value
UARTConfigPrintf(DEBUG_UART_BASE, "REG1(0x4845B804): %08X\n", HW_RD_REG32(0x4845B804));

/* 3.B. Program Stop States */
HW_WR_REG32(0x4845B314, 0x00004197); // CAL_CSI2_TIMING_0
// STOP_STATE_COUNTER_IO1 = 0x197
// STOP_STATE_X4_IO1 = 0
// STOP_STATE_X16_IO1 = 1
UARTConfigPrintf(DEBUG_UART_BASE, "CAL_CSI2_TIMING_0 (0x4845B314): %08X\n", HW_RD_REG32(0x4845B314));

/* 4. Force FORCERXMODE */
dwTmp = HW_RD_REG32(0x4845B314);
dwTmp |= 0x00008000;
HW_WR_REG32(0x4845B314, dwTmp);
UARTConfigPrintf(DEBUG_UART_BASE, "CAL_CSI2_TIMING_0 (0x4845B314): %08X\n", HW_RD_REG32(0x4845B314));

/* E. Power up the PHY using the complex IO */
dwTmp = HW_RD_REG32(0x4845B304);
dwTmp |= 0x08000000; // PWR_CMD = 1
HW_WR_REG32(0x4845B304, dwTmp);
UARTConfigPrintf(DEBUG_UART_BASE, "CAL_CSI2_COMPLEXIO_CFG_0 (0x4845B304): %08X\n", HW_RD_REG32(0x4845B304));

/* F. Wait for power up completion */
for(dwTmp = 0;dwTmp < 10;dwTmp++)
{
if((HW_RD_REG32(0x4845B304) & 0x02000000) != 0)
break; // Waiting for Power On
Osal_delay(1);
}
if(dwTmp < 10)
UARTConfigPuts(DEBUG_UART_BASE, "CSI-2 Powered Up\n", -1);
else
UARTConfigPuts(DEBUG_UART_BASE, "CSI-2 timeout\n", -1);

//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

As a result CSI-2 powered up well. Then I start up the CSI2 source (1080p) and waiting for flag RESET_DONE.

//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

/* 2. Wait for reset completion */

for (dwTmp = 0; dwTmp < 250; dwTmp++)
{
dwReg = HW_RD_REG32(0x4845B304);
if((dwReg & 0x20000000) != 0) // CAL_CSI2_COMPLEXIO_CFG_0 (RESET_DONE bit)
break;
Osal_delay(1);
}
if(dwTmp < 250)
UARTConfigPuts(DEBUG_UART_BASE, "CSI-2 Complex IO Reset Done\n", -1);
else
UARTConfigPuts(DEBUG_UART_BASE, "CSI-2 Reset timeout\n", -1);

//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

But flag doesn't set. Is this the problem with a signal or it's wrong initialization sequence?

Thank you for your help in advance!

Regards, Andrei

over 6 years ago

0 lding over 6 years ago

TI__Guru* 95265 points

Hi,

Sorry we don't have CSI2 driver in RTOS and can't provide much input here. Please consider using the Linux OS, or trying to port Linux code into RTOS as you did. As you can't see the flag set, please make sure the Linux driver worked and use the same signal input to rule out the signal problem. As for the initialization sequence, please refer to TRM.

Regards, Eric

0 German Baranov over 6 years ago

Intellectual 660 points

Hi!

I'm not sure if it's your case, but might be the following:

To complete reset, CSI receiver has to see STOP STATE (LP11, I think) on all MIPI lines, including MIPI clock.

If you started your image sensor to early, and keep only data lines in stop, but clock is running, your CSI PHY

will not complete reset.

Put sensor in sleep and turn it on right before "wait for reset"

Regards

0 Andrei Kolganov over 6 years ago in reply to German Baranov

Intellectual 275 points

Hi, German,

I have the following below configuration of lanes:
dx2, dy2 - clock lane
dx1, dy1 - data 0 lane
dx0, dy0 - data 1 lane

At the beginning all lanes of CSI-2 I hold at the level 1,2V. Then I write the registers of CSI as shown below:

CAL_CSI2_CTX0_0(0x4845B330): 1

CM_CAM_CAL_CLKCTRL(0x4A009028): 40001
CAL_CSI2_COMPLEXIO_CFG_0(0x4845B304): 123
CTRL_CORE_CAMERRX_CONTROL(0x4A002E94): 26400
CAL_CSI2_COMPLEXIO_CFG_0(0x4845B304): 40000123
REG0(0x4845B800): 1000427
REG1(0x4845B804): e002e10e
CAL_CSI2_TIMING_0 (0x4845B314): 4197
CAL_CSI2_TIMING_0 (0x4845B314): c197
CAL_CSI2_COMPLEXIO_CFG_0 (0x4845B304): 48000123
CSI-2 Powered Up
CAL_CSI2_COMPLEXIO_CFG_0 (0x4845B304): 4a000123

CSI_2_Start_Streaming()
Delay_100_ms()
Check_For_Reset_250_ms()

CSI-2 Reset timeout
CAL_CSI2_COMPLEXIO_CFG_0 (0x4845B304): 4a000123

As you wrote I start the sourse before checking loop for reset: Check_For_Reset_250_ms().

The reset status is invalid.

I supply clock and two data lanes as I can't supply only clock lane. May be is that reason?

I acctualy don't understand what does "byte clock" mean. Is this the frequency CSI-2_clock_lane / 8?

Can I supply normal video signal via all lanes in this case?

Regards

0 German Baranov over 6 years ago in reply to Andrei Kolganov

Intellectual 660 points

Hi!

Haven't you tried to release COMLEXIO reset later? In your sequence

How about to move it to the point after "CSI-2 Powered Up"?

Something like that

CAL_CSI2_COMPLEXIO_CFG_0 (0x4845B304): 8000123
CSI-2 Powered Up
CAL_CSI2_COMPLEXIO_CFG_0 (0x4845B304): 4a000123

b) I keep all MIPI lines in LP00 (0V) until after compexio reset release.

That is, it looks like that:

MIPI -> LP00

Hold COMPLEXIO in reset

initialize and power up CSI PHY

release COMPLEXIO reset

MIPI -> LP11

(In that point we suppose to run FORCERX stuff, but I observe driver which works without it. Sometimes

I think that FORCERX is just TI guy's joke to have fun on designers)

start transmission

check for reset

I don't know if this LP00 state is really required. My attempts to get answers from TI

about require states of MIPI lines during initialization failed.

c) "byte clock"

From MIPI spec

The RxByteClkHS is generated
by dividing the received High-Speed DDR clock

Unless TI invented their own meaning

(Only not "/8", but "/4" -we have DDR bus here)

Regards

0 Frank Livingston over 6 years ago in reply to German Baranov

TI__Mastermind 30108 points

Hi German,

>> Can we get probably more detailed instructions then in spruhl6a with requirements to signals and timing, if they exist?

Can you please create a separate thread for this topic rather than hijacking this thread? This thread started out as an RTOS thread, but your question is more about hardware documentation. A separate thread will make it easier to track this related, but separate topic.

Thanks,
Frank

0 German Baranov over 6 years ago in reply to Frank Livingston

Intellectual 660 points

OK, I removed d) paragraph, never mind about it

0 German Baranov over 6 years ago in reply to German Baranov

Intellectual 660 points

Hello!

Below is my vision of TI's CSI PHY start procedure.

I'm not related to TI. This is my personal experience, it can contain mistakes.

I'm working with DM385 processor, but I think CSI procedures can be similar in some other cases.

Starting TI's CSI PHY COMPLEXIO.

TI processor in this setup is CSI receiver and another device,
let's call it Image Sensor, or just Sensor, is transmitter.

Suppose total reset of CSI module in processor is already done,
we are activating COMPLEXIO.

1) Put all your CSI lines to LP00 state. If your Sensor drives
LP00 actively, then turn on this state; or, power off the Sensor
and turn on pull-down resistors in PHY. ISS guide tells you to
use pull-downs, without mentioning final purpose of the operation -
LP00 on all lines. About turning on pull-downs see 2)

2) Enable required by you CSI lines and connect pull-downs (this is
done in the same register). CONTROL_CAMERA_Rx register, as I
understand, is not part of ISS. That's why it is mentioned in
ISS guide, but not described there. Look for this register
description in TechRef for your processor, in CONTROL MODULE
chapter. It also, probably, differs, from processor to processor;
at least in my case, bit values, given in ISS guide differ
completely from ones in my Tech Ref and my reality. (Use Tech Ref).
One more thing. Be careful with driver from TI RDK. I've found
in the middle of the file iss_init.c next line of code:

*(unsigned int *) 0x4814069C = 0xAAAAA2c;

without any comments and variable names. That was CONTROL_CAMERA_Rx
configuration that did not correspond to my setup and screwed up
my efforts to start device until I recognized it.

3)Reset RESET_CTRL bit in CSI2_COMPLEXIO_CFG to 0 (MIPI lines are still
in LP00)

4)Config COMPLEXIO: set lines in CSI2_COMPLEXIO_CFG,
power up COMPLEXIO by PWR_CMD in CSI2_COMPLEXIO_CFG
and check power status;
do other configurations, like interrupts.

5) Release COMPLEXIO reset by setting RESET_CTRL bit in
CSI2_COMPLEXIO_CFG to 1 (MIPI lines are still in LP00)

6) Turn on Sensor. All MIPI lines will be put to LP11 for some time
by CSI transmitter automatically.

There is FORCERX process after stage 5-6). When strictly following ISS guide,
you have to start FORCERX after stage 6) by setting to 1
FORCE_RX_MODE_IO bit in CSI_TIMING register, and wait until it is 0,
this means CSI bus lines are in LP11. After that, begin process of
checking RESET_CTRL. In the driver I got with TI_RDK,
FORCE_RX_MODE_IO is simply forced to 0, and small delay is kept after
powering on Sensor. Both ways work.

7) Now Sensor starts "Procedure to Initiate High-Speed Clock Transmission"
(as it is called in MIPI D-PHY spec), which is sequence similar to
MIPI HS Data start just on the clock lines (LP11-LP10-LP00-HS0-CLK).
If CSI receiver catches the procedure successfully, it goes out of reset
with COMPLETED bit in CSI2_COMPLEXIO_CFG set and
RESET_DONE field in ISS_CSI2_PHY_REGISTER1 in 11b state.
In start of data transmission process all timings are related to MIPI clock.
In clock start, MIPI clock is not available to CSI receiver yet,
that's why receiver time settings relate to internal clock called
CAM_PHY_CTRL_FCLK. Because of different clock sources for timings in
CSI receiver and transmitter, you might have to do timing adjustments
to obtain successful reset. (For instance to play with Tclk-prepare or
Tclk-zero in Sensor settings).

0 Andrei Kolganov over 6 years ago in reply to German Baranov

Intellectual 275 points

Hi, German,

Thanks for your support!

I tride your variant of sequence of initialization but when I do point 4 power status failed. In my case it works if finaly I make point 5. It seems that I have other SoC.

Then I'll try to set up module under Linux and I'll have a look inside setup process by emulator. Maybe this problem with CSI-2 signal level.

I'll inform you by email some later

Kind regards,

Andrei

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AM5708: CSI2 PHY setup problem