TMS320C6678: HyperLink SerDes PLL Configuration Register - MPY field specification issue?

Let me take a look at this and I will provide my feedback.

Best Regards,
Yordan

Also please note that there is one more mistake in the sprugw8c.pdf, chapter 2.1 Clock Control

The value of the reference clock (third value) should be 312.5 MHz and the the manual is specified as 315MHZ

HyperLink needs a reference clock for its SerDes module. The reference clock can be of
the following frequencies:
• 156.25 Mhz
• 250 MHz
• 312 MHz

And I have the third question.

Why the last 2 bits for HYPERLINK_SERDES_CFGPLL[MPY] are different when we have multiplication factors with half of the unit?

For MPY=12.5X we have 00110010b -> the last 2 bits are 10

For MPY=16.5X we have 01000001b -> the last 2 bits are 01

Any conclusions about these typos?

Hi,

Sorry, I missed this.
For your first two remarks, I think you are correct. There seems to be a mistake in the documentation. 

For the last question:
  "Why the last 2 bits for HYPERLINK_SERDES_CFGPLL[MPY] are different when we have multiplication factors with half of the unit?"

I am not sure about this. Will consult the design team.

Best Regards,
Yordan