Hi,
Our customer is designing a board using DDR3.
Are there any data on Timing Budget within the same Net Classes regarding DDR signal wiring?
Best Regards,
Kouji Nishigata
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Hi,
Our customer is designing a board using DDR3.
Are there any data on Timing Budget within the same Net Classes regarding DDR signal wiring?
Best Regards,
Kouji Nishigata
Hi,
Please follow the guidelines in section 7.7.2.3 of the AM335x Datasheet Rev. K.
Hi,Biser
Thank you for answering.
I'm looking at dataSheet, but this is mainly about wire length.
Customers measure timing in simulations, but they are ultimately seeking criteria for how much delay time is acceptable.
As I heard in the answer about DDR_CKE, if they follow the Routing Specification, do they have to know about the timing budget for time?
Best Regards,
Kouji Nishigata
Kouji, to simplify design for customers, we have provided design guidelines in the datasheet which will ensure proper timing. As long as your customer follows the board design guidelines, they should not have to worry about timing budgets.
Regards,
James