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Original question:

TMS320C6678: HyperLink SerDes PLL Configuration Register - MPY field specification issue?

TMS320C6678: TMS320C6678: Hyperlink interrupts versus data synchronization

Daniel Costin
Intellectual 610 points
Part Number: TMS320C6678


Hi,

      1. Considering I have 2 C6678 boards and I want to create a hyperlink communication in both sides.

      As data transfer method I have 3 methods QMSS, EDMA, CPU direct access. In any of the cases I want to know what methods of synchronization I have for the data traffic between these  boards. If I write some data to remote how will be the remote notified that data is available in all 3 methods ( QMSS, EDMA, CPU direct access).

       How will know the sender that remote node read the data? I should be notified somehow to prevent sender to write a new data in that segment and to overwrite information before remote part to read it, right?

      I read the comments from https://e2e.ti.com/support/processors/f/791/p/193417/839313?tisearch=e2e-sitesearch&keymatch=hyperlink%2520interrupt#839313

      2. If I want to use the simplest data transfer method (from complexity and configuration point of view), CPU direct access, I tried to follow the PDK example and I am a little bit confused: What is the difference between hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE and hyplnk_EXAMPLE_TEST_CPU_BLOCK_XFER

     3. How can I generate from any core of evmA an interrupt to any core of evmB? If I want to signal evmB (core 1 as example) with an interrupt from evmA (core0 as example) as new data is available how should I do this? Can I use something from this hypelink interrupt part to generate back to evmA that data was read and I am ready for new data? Also how can I distinguish if the interrupt is for new data available or if it is a acknowledge interrupt?

    4. From your PDK example: I suppose dataBufferViaHlink is some address from 0x40000000 - 0x4FFFFFFF range where sender should write data for the remote side. Why do you have this offset calculation: segmentID<<(RXAddrSel.rxSegSel+16)

*dataBufferViaHlink = (void *)( (char *)hlinkBase + globalAddrOffset + (segmentID<<(RXAddrSel.rxSegSel+16)));

/Daniel.

  • 0
    TI__Guru* 95265 points

    Hi,

    Q1. This is a common issue for data sync between two devices connected via some peripherals. If you expect the data changes every time at certain location (e.g, you wrote a counter at the end of data block), you can pull the location. Or, the sender can send an interrupt to the receiver via Hyperlink after Tx the data, so the Rx side can be notified. Even, this sync can be done from other means in the system, e.g.using a GPIO interrupt. This applies how the receiver knows there are data came in, so it can process. And how the sender knows the Rx side already consumed the data, it can send the next block.

    Q2.  To me this is one token (32-bit) and a block data (multiple 32-bit), no big difference.

    hyplnk_EXAMPLE_TEST_CPU_TOKEN_EXCHANGE, 

    /*****************************************************************************
    * Pass one "token" by writing to the "write" address then attempting
    * to read the same value back via the "read" address.
    *
    * The CPU generates the transactions
    *
    * 0: pass
    * 1: fail
    ****************************************************************************/

    hyplnk_EXAMPLE_TEST_CPU_BLOCK_XFER

     

    /*****************************************************************************
    * Write a block of data to remote side then verify it
    *
    * The CPU generates the transactions via memcpy and memset
    *
    * 0: pass
    * 1: fail
    ****************************************************************************/

    Q3. The TI Processor SDK RTOS Hyperlink example doesn't support interrupt except for error interrupt. There is no development work for it. You need to look for some E2E discussion and Hyperlink user guide for some development/debug work. I did a CCS project for this here: https://e2e.ti.com/support/processors/f/791/t/806548 you can refer to.

    As for the idea how to generate to EVMB core1 from EVMA core 0. The EVMA core 0 runs the Hyperlink example and generate an interrupt, transmitted to remote side, the Rx side also runs an Hyperlink example, you need to routine the received interrupt to core 1 instead of core 0. Please check the 6678 DATA SHEET Figure 7-32 TMS320C6678 System Event Inputs — C66x CorePac Primary Interrupts (Sheet 1 of 4). Select an CICx_output can go to any core. 

    Also some reading material: http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices

    Q4. This is example code and we want to use an offset into the Hyperlink memory space for each segment (we used 0, 5, 7 as segmentID), so they are not overlapping.  

    Regards, Eric

  • 0 in reply to lding
    Intellectual 610 points

    Hi Eric,

      Thank you for your response.

       1. My question was: how I could know after sender transmitted data if the receiver already consumed it. This is important into a peer traffic scenario because sender is writing to the same memory region (segment space for Hyperlink) and it is unwanted to overwrite the transmitted data without having a consumer in synch. Your answer was: " And how the sender knows the Rx side already consumed the data, it can send the next block."

       I do not understand your state: what is the relation of sending the next block from transmitter part with the fact that I should know if the receiver consumed or not the data.

    3. For the interrupt mechanism: I see there are 4 registers that could be used for interrupting 2 EVMs through Hyperlink, but the description is so limited and it is impossible to understand what values must be programmed for targeting a specific behavior. I refer to Interrupt Control Index, Interrupt Control Value, Interrupt Pointer Index and Interrupt Pointer Value.

       For me it is important to know what should I set for these registers and how I could get notified with these registers if I want to differentiate  different IDs from various field with different segments or sender IDs. I see icidx could be set between 0 and 63, but it is not specified what means this range and how could be interpreted. Is the value of this field related to local or remote evm?

       For what can be used the Interrupt Pointer Value Register. 

       Supposing that I could made a logic agreement: core0 is always sending to some region mapped to a remote rx segment and so on... Could I use the above 4 interrupt registers to signal by different event or ids if sender already wrote something? Will this event wakeup all the cores or I could select a specific core?

    /Daniel

  • 0 in reply to Daniel Costin
    TI__Guru* 95265 points

    Daniel,

    For 1, "And how the sender knows the Rx side already consumed the data, it can send the next block." =======> Sorry my typo, I meant that the receive side can send an interrupt to the Tx side, after processing the received data.

    For  3, I also explained in https://e2e.ti.com/support/processors/f/791/t/848160, this needs some read of the user guide and experiment. "Could I use the above 4 interrupt registers to signal by different event or ids if sender already wrote something? Will this event wakeup all the cores or I could select a specific core?" =====>Yes, you can use an interrupt with different event IDs. This only wake-up one core that the interrupt routed to.

    Regards, Eric