AM3358: DDR3 data integrity check fails

Hi,

You need also to do the procedure described here: processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

Hi Biser,

  Thanks for the reply.

       I did the DDR Software Leveling also, that GEL file value only i shown above. But still i am getting error while running DDR data transfer check  

      CortxA8: GEL Output: No of Failed locations are :: 0x00000027 

       CortxA8: GEL Output: Data Integrity check Failed

    pls find the attachment of AM335x_EMIF_Configuration_Tool.xlxs which i have calculated the ddr value for IS43TR85120B-125KBLI DDR RAM.

   while running AM335x_DDR3_SlaveRatioSearch.out i given below input which i got from 3E value of spreadsheet

[CortxA8] 

Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
1

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
113

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
86

after many iteration i got final value as below

  ***************************************************************

The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO 0x046 | 0x03c | 0x041 | 0x00a
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x0e1 | 0x0c7 | 0x0d4 | 0x01a
DATA_PHY_WR_DQS_SLAVE_RATIO 0x0d7 | 0x0c9 | 0x0d0 | 0x00e
DATA_PHY_WR_DATA_SLAVE_RATIO 0x117 | 0x109 | 0x110 | 0x00e
***************************************************************
rd_dqs_range = 1
fifo_we_range = 1
wr_dqs_range = 1
wr_data_range = 0

Optimal values have been found!!

***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO 0x046 | 0x03c | 0x041 | 0x00a
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x0e1 | 0x0c7 | 0x0d4 | 0x01a
DATA_PHY_WR_DQS_SLAVE_RATIO 0x0d7 | 0x0c9 | 0x0d0 | 0x00e
DATA_PHY_WR_DATA_SLAVE_RATIO 0x117 | 0x109 | 0x110 | 0x00e
***************************************************************

===== END OF TEST =====

In ddr configuration document mension 

• if (DDR_CK length) < (DDR_DQS length), program this register to 1
• If (DDR_CK length) > (DDR_DQS length), program this register to 0 

      For mycase DDR_CK is higher than DDR_DQS but spreadsheet show  CMDx_PHY_INVERT_CLKOUT = 1, I can't able to edit the value for that because its a protected cell. pls look into that also. i am using EVM v1.6A board file

pls advice me how to resolve it.

Regards,

Jagadeesh

AM335x_EMIF_Configuration_Tool.xlsx

Jagadeesh, the earlier link quoted is in the process of being deprecated.  Can you please try downloading the app note that is associated with the AM335x EMIF tool.    www.ti.com/.../sprack4

The link in the Intro section will link to a zip which has an updated software leveling algorithm.  Follow the instructions in Section 3 (they are similar to what you have already done) to run the software leveling algorithm to get optimal values.  Then test with those values.

If you are still having problems, we may need to look at your board layout

Regards,

James

Hi James,

          I have follwed same document only. Also i used  AM335x_GPEVM_ZCZBASEBOARD_3H0002_LAYOUT_REV1_6A board file. Only different RAM chip,  remains everything same as the board file.

still i am getting failed in RAM data check. 

In AM335x_EMIF_Configuration_Tool.xlsx, step3-board details sheet CMDX_REG_PHY_INVERT_CLKOUT value always 1 even CLK trace lenth higher than DQQS trace

pls conform the value of CMDX_REG_PHY_INVERT_CLKOUT

Regards,

Jagadeesh

Jagadeesh, yes, INVERT_CLKOUT should remain 1 regardless of CLK to DQS trace length.  To help debug your problem, can you run the following DDR analysis script from here:  

git.ti.com/.../am335x-ddr-analysis.dss

Instructions for running the script is here:  git.ti.com/.../README

Can you also send your full GEL file you are using to configure your board.

Regards,

James

Hi james,

     i run the DDR analysis script and i have attached the output file of DDR analysis script and GEL file. pls find it.

AM335x_forSlaveRatio.gel

Switched to DAP_DebugSS
Read value of 2b94402e from Device_ID register.
CONTROL: device_id = 0x2b94402e
  * AM335x family
  * Silicon Revision 2.1

CONTROL: control_status = 0x00400318
  * SYSBOOT[15:14] = 01b (24 MHz)
CM_CLKSEL_DPLL_DDR = 0x00003202
  * DPLL_MULT = 50 (x50)
  * DPLL_DIV = 2 (/3)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 24 MHz
 -> CLKOUT_M2 = DDR_PLL_CLKOUT = 400 MHz

EMIF: SDRAM_CONFIG = 0x61a053b2
  * Bits 31:29 (reg_sdram_type) set for DDR3
  * Bits 28:27 (reg_ibank_pos) set to 0
  * Bits 26:24 (reg_ddr_term) set for RZQ/4 (001b)
  * Bits 22:21 (reg_dyn_odt) DDR3 dynamic ODT set to RZQ / 4
  * Bit  20    (reg_ddr_disable_dll) set to 0, DDR3 DLL enabled
  * Bits 19:18 (reg_sdram_drive) set for RZQ/6 (00b)
  * Bits 17:16 (reg_cwl) set for 0, CWL = 5
  * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface
  * Bits 13:10 (reg_cl) set to 4 -> CL = 6
  * Bits 09:07 (reg_rowsize) set to 7 -> 16 row bits
  * Bits 06:04 (reg_ibank) set to 3 -> 8 banks
  * Bits 02:00 (reg_pagesize) set to 2 -> 10 column bits

EMIF: PWR_MGMT_CTRL = 0x00000000
 * Bits 10:8 reg_lp_mode set to 0, auto power management disabled
 * Warning: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
   -> Please see the silicon errata (DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit) for more details.
   -> This is only an issue if used in conjunction with reg_lp_mode=2.

DDR PHY: DDR_PHY_CTRL_1 = 0x00100208
  * Bits 9:8 (reg_phy_rd_local_odt) to 2 -> full thevenin termination
  * Bits 4:0 (reg_read_latency) set to 8 -> Ok: CL+2 is typical with PHY_INVERT_CLKOUT=1.

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x61a053b2
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x00000c30
*(0x4c000014) = 0x00000c30
*(0x4c000018) = 0x0aaad4d3
*(0x4c00001c) = 0x0aaad4d3
*(0x4c000020) = 0x246b7fda
*(0x4c000024) = 0x246b7fda
*(0x4c000028) = 0x50ffe67f
*(0x4c00002c) = 0x50ffe67f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x0000007f
*(0x4c000084) = 0x00000025
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0xf8eadcfc
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x500750c6
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00100208
*(0x4c0000e8) = 0x00100208
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x0000018b
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD1_IOCTRL = 0x0000018b
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD2_IOCTRL = 0x0000018b
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA0_IOCTRL = 0x0000018b
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA1_IOCTRL = 0x0000018b
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010167
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000001
  * CKE controlled by EMIF (normal/ungated operation).

Regards,

Jagadeesh

Hi Jagadeesh, i don't see any clues yet as to why you are seeing errors.  Can you send the DDR schematic portion of your design?

Aside from doing the integrity check, can you open up a memory window in CCS at 0x80000000, and perform some random peek/poke operations in the memory to see what the behavior is? 

Regards,

James  

Hi James,

        In open memory browser, the values are automatically changing without doing anything.  

DDR schematic portion below pls find it.

AM335x_HDM.pdf

Regards,

Jagadeesh

Hi James,

        In memory browser, the values are automatically changing without doing anything.  

DDR schematic portion below pls find it.

1731.AM335x_HDM.pdf

Regards,

Jagadeesh

Hi James,

        In open memory browser, the values are automatically changing without doing anything.  

DDR schematic portion below pls find it.

4760.AM335x_HDM.pdf

Regards,

Jagadeesh

Jagadeesh, I'm still not seeing any issues at the moment.  In fact, as you stated, it looks like its a carbon copy of the GP EVM design.

-Can you check for proper voltages throughout, including VREF, VTT, and VDDS_DDR?

-Can you post the processor side schematic for the DDR?

-Other than the different memory, are there any other differences from the GP EVM in the DDR design?  Power supply, layout, etc.

-As a test, can you try the AM3358 GP EVM GEL as is from CCS, without any modifications.

Regards,

James  

Hi James,

I checked all voltage line 

 VDD_VREF = 0.74V

 VDDR_VTT  = 0.74V

 VDDS_DDR = 1.49V

i didn't change anything on the EVM design RAM chip changed and added some TTL to RS232 converter on my board

i run the GEL file form CCS that also same error 

schematic is bleow pls find it

0184.AM335x_HDM.pdf

Regards,

Jagadeesh

Thanks Jagadeesh.

-Have your ruled out an assembly problem?  Do multiple boards exhibit the same issue?

-You may have to double check that your board design files match the schematic.  We have seen sometimes in the past that this is not the case, and misconnections are not apparent on the schematic.  

-Were all the design rules followed in the datasheet, especially including skew and trace length limitations?

Regards,

James

Hi James,

      I have checked board file with schematic pin to pin connection for the DDR section and power everything fine.

this is skew for ddr lines..

 Regards,

Jagadeesh

Hi Jagadeesh,

Some questions and things to try:

-Based on your inputs in the spreadsheet you provided, your processor to byte1 CLK length is 1.399, while processor to byte0 length is 2.130.  This is a difference of 0.731, which violates the A3 length spec of 660mils in table 7-66 of the datasheet.

-Based on the info provided, i can't tell if some of the other parameters in the same table were violated.  This may be contributing to some of your issues.

-looking at table 7-67, it looks like you may be slightly violating the DQS to DQ skew, which is 25mils.  Similarly, you are slightly violating the DQS skew of 5mils.  Also realize that number of vias and center to center spacing can also be contributing to the issues.

-Can you try increasing the read latency to 9 in the GEL and re run the DDR initialization to see if you get more stable results.  

-Can you try reducing the DDR speed to 303MHz and re run the DDR initialization to see if you get more stable results.  You can do this in the GEL in function ARM_OPP100_Config() by changing DDR_PLL_Config(CLKIN,23,303,1)

-When you run the SlaveRatioSearch.out file, can you confirm that this file is dated 2019?

-Can you post the full output of the SlaveRatioSearch algorithm.  I'd like to see the progression of the convergence.

Regards,

James