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CCS/TDA2EG-17: TDA2E-17 using SRV+CBB function. LCD display will flick.

Tao Han
Expert 6855 points

Part Number: TDA2EG-17

Tool/software: Code Composer Studio

Hi experts:

We develop SRV+CBB at TDA2E-17. When we run full function LCD will flick and just run single function.

LCD flick will disappear. Maybe it is A15 and DSS module conflict at access DDR3 memory.

Or Maybe it is A15 display have some problem. We are not sure and can you give us some suggest about this problem?

Attached are the test summary and bandwidth number.LCD_flick_e2e.pdf

Best Regards!

han tao

  • 0
    TI__Mastermind 30245 points

    Hi Han

    Couple of things to check:

    1. Is the DSS MFLAG settings enabled? Registers to check: DISPC_GLOBAL_MFLAG_ATTRIBUTE, DISPC_VID1_ATTRIBUTES, DISPC_VID2_ATTRIBUTES, DISPC_VID3_ATTRIBUTES, DISPC_GFX_MFLAG_THRESHOLD, DISPC_VID1_MFLAG_THRESHOLD, DISPC_VID2_MFLAG_THRESHOLD, DISPC_VID3_MFLAG_THRESHOLD

    2. Is the DDR set at 666 MHz or 532 MHz? - Check the DDR PLL configuration in the SBL

    3. Are any bandwidth limiters set on the GPU? - Base address 0x4480 5B00 and 0x4480 5C00, Read offsets 0x0 to 0x14.

    4. What is the value of EMIF_OCP_CONFIG?

    Thanks and Regards

    Piyali

  • 0
    TI__Guru**** 502325 points

    Hi Tao,

    When you say flic, you mean flicker? 

    From the presentation, it looks like if you reduce bandwidth, the issues goes away, can you please confirm? 

    Rgds,

    Brijesh

  • 0 in reply to Piyali Goswami
    Prodigy 210 points

    root@(none):~# omapconf --force dra72x read 0x5800185C
    00000006


    root@(none):~# omapconf --force dra72x read 0x580010CC
    82288A61


    root@(none):~# omapconf --force dra72x read 0x5800115C
    86288879

    root@(none):~# omapconf --force dra72x read 0x58001370
    8A288A61

    root@(none):~# omapconf --force dra72x read 0x58001860
    00000000

    root@(none):~# omapconf --force dra72x read 0x58001864
    00000000

    root@(none):~# omapconf --force dra72x read 0x58001868
    00000000

    root@(none):~# omapconf --force dra72x read 0x5800186C
    00000000


    root@(none):~# omapconf --force dra72x dump 0x44805B00 0x44805B14
    |----------------------------|
    | Address (hex) | Data (hex) |
    |----------------------------|
    | 0x44805B00 | 0x002C0001 |
    | 0x44805B04 | 0x00D026C7 |
    | 0x44805B08 | 0x00000002 |
    | 0x44805B0C | 0x00000005 |
    | 0x44805B10 | 0x00000000 |
    | 0x44805B14 | 0x00000000 |
    |----------------------------|

    root@(none):~# omapconf --force dra72x dump 0x44805C00 0x44805C14
    |----------------------------|
    | Address (hex) | Data (hex) |
    |----------------------------|
    | 0x44805C00 | 0x002C0001 |
    | 0x44805C04 | 0x004D9BCD |
    | 0x44805C08 | 0x00000002 |
    | 0x44805C0C | 0x00000005 |
    | 0x44805C10 | 0x00000000 |
    | 0x44805C14 | 0x00000000 |
    |----------------------------|


    root@(none):~# omapconf --force dra72x read 0x4C000054
    0A500000

  • 0 in reply to liu wang
    Prodigy 210 points

     DDR set at 666Mhz

  • 0 in reply to liu wang
    TI__Expert 6855 points

    Hi liu wang:

    Please change the DSS priority and try it again.

    Thanks a lot!

    Han Tao

    omapconf --force dra72x write 0x580010CC 0x82A88A61
    omapconf --force dra72x write 0x5800115C 0x86A88879
    omapconf --force dra72x write 0x58001370 0x8AA88A61
    omapconf --force dra72x write 0x580010A0 bit 14 set 1.

    omapconf --force dra72x write 0x58001860 0x03000200
    omapconf --force dra72x write 0x58001864 0x06000400
    omapconf --force dra72x write 0x58001868 0x06000400
    omapconf --force dra72x write 0x5800186C 0x06000400

  • 0 in reply to Tao Han
    TI__Expert 6855 points

    Hi Experts:

    Compare old SDK and 3.07 SDK.

    change 0x5800185C from 0x6 to 0x5. The problem resolved, LCD flicker disappear.

    Question 1: Setting GLobal MFLAG to debug mode, Does it have risk?

    Question 2: Could you please tell me why 3.07 RDK add those modify MFLAG's code like below picture?

    Best Regards!

    Han Tao

    1. change MFLAG to debug bit

    2. RDK default setting code at display link

  • 0 in reply to Tao Han
    TI__Expert 6855 points

    Hi Team:

    Please check the feedback about setting MFLAG to 0x5 and 0x6 different.

    Question 1: 0x5 means DSS always on. There is no risk in setting MFLAG to always on mode. This essentially means display always gets priority, even if display internal FIFO have sufficient data.

    Question 2: change 0x5 to 0x6 reason is  we have set the display FIFO thresholds such a way that we could enable dynamic FIFO. Could you also please check if FIFO thresholds are setup correctly? If they are not set, dynamic MFLAG may not work.FIFO threshold is set in the register MFLAG_THRESHOLD. We believe Dynamic MFLAG is a better way to go with the thresholds tuned for the usecase 50% and 75% have been found to be good for most applications.

    Best regards!

    Han Tao