CCS/66AK2G12: About EMIF control registers

user5968673

Intellectual 430 points

Part Number: 66AK2G12

Tool/software: Code Composer Studio

Dear Sir,

We are looking for the EMIF control registers.

Is there a register to exchange DQ paired with DQS and DQM?

I want to control the following pins as a pair by switching DQ.

・DDR3_DQS0_P / DDR3_DQS0_N / DDR3_DQM0 / DDR3DQ[8:15]

・DDR3_DQS1_P / DDR3_DQS1_N / DDR3_DQM1 / DDR3DQ[0:7]

Best regards.

over 6 years ago

0 Rahul Prabhu over 6 years ago

TI__Guru** 116960 points

I have looped in the DDR expert to comment on this query but please review the DDR3 Design guidance document for Keystone devices for DQ/DQS/DQM setup

http://www.ti.com/lit/an/sprabi1c/sprabi1c.pdf

http://www.ti.com/lit/an/sprabx7/sprabx7.pdf

We expect customers to use the DDR EMIF Tool provided with the Keystone II DDR Initialization for generating values for EMIF and EMIF PHY register.

Regards,

Rahul

0 user5968673 over 6 years ago in reply to Rahul Prabhu

Intellectual 430 points

Dear　Rahul,

Thank you for reply.

About Table 14 of DDR3 Design Requirements for KeyStone Devices,

Is this Table meaning each Data Group paired DQ and DQS and Data Mask?

That is to say, Is it meaning the DQ can not change DATA grounp?

Best regards.

0 Bill Taboada over 6 years ago in reply to user5968673

TI__Mastermind 42545 points

Hi,

The signals for each byte lane must be kept together and connected to the proper byte lane on the memory device. You cannot assign the DQSx signals to a different data byte lane. If you have connected the DQS signals to the wrong byte lane on your board you will have to update the board to fix the problem. This was discussed in an earlier post linked below.

https://e2e.ti.com/support/processors/f/791/t/852328

Regards, Bill

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CCS/66AK2G12: About EMIF control registers