TMS320C6678: TMS320C6678: Cppi_open initialization + memory region configurations

Daniel Costin

Part Number: TMS320C6678

Hi,

There are many Hyperlink + CPPI examples on this forum. All of these examples are using the below initialization for CPPI:

/* Set up QMSS PKTDMA configuration */
memset ((void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));
cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA;
cpdmaCfg.qm1BaseAddress = 0x34030000;//local QM area
cpdmaCfg.qm2BaseAddress = 0x40000000;// vUSR remote QM area

/* Open QMSS PKTDMA */
cppiHnd = (Cppi_Handle) Cppi_open (&cpdmaCfg);

- Can you please detail what is the reason of setting qm1BaseAddress and qm2BaseAddress and not qm0BaseAddress and qm1BaseAddress ?

- Can you please detail why you set qm1BaseAddress = 0x34030000? What is setting this value from QM for hyperlink data transfer?

- Are these qmxBaseAddress values related to memory regions and queues?

The below code snippet is from Hyperlink_config where are configured the RX segments

/**** local vUSR Tx, Rx address mapping for remote DSP
* 0x40000000 => 0x34020000 and 0x40200000 ==> 0x0C010000 **/
configure_address_mappings(0xD, 4,(Uint32)0x34020000,(Uint32)0x0C010000);

In all these examples there is a function called configure_remote_address_mappings() never used. It should configure from one EVM the registers of second eVM to make this example to work?

For reference see the source code: https://e2e.ti.com/support/processors/f/791/t/176863

- As regards the memory region configuration: When you have many memory regions configured, what is the value that need to be setup for monoMemInfo.startIndex field? Is this field incremented with the value of monoMemInfo.descNum from previous memory region?

/Daniel

over 6 years ago

0 lding over 6 years ago

TI__Guru* 95265 points

Hi,

I need to study this example and give back to you in a few days. For Hyperlink, we use the CPU or EDMA in most of the case, certainly you can use Infrastructure DMA but almost nobody uses it.

Also the code I saw is,

/* Set up QMSS CPDMA configuration */
memset ((Void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg));
cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA;
cpdmaCfg.qm0BaseAddress = QMSS_DATA_ADDR; //local QM area
cpdmaCfg.qm1BaseAddress = QMSS_DATA_ADDR + 0x00010000; //local QM area
cpdmaCfg.qm2BaseAddress = remoteQMSSPtr; //remote QM area
if(debug)printf ("Remote Queue Pointer for qm2BaseAddress 0x%p\n", remoteQMSSPtr);

That is, qm0BaseAddress is used, please make sure refer to the TI PRSDK example code for this.

Regards, Eric

0 Daniel Costin over 6 years ago in reply to lding

Intellectual 610 points

Hi Eric,

The code pointed by me is also delivered by TI. However, the question is applicable for official hyplnk example from pdk.

The cpdmaCfg.qm2BaseAddress is initialized with the mapped address from 0x40000000 - 0x4FFFFFFF region, but I don't understand what's the reason of cpdmaCfg.qm0BaseAddress = QMSS_DATA_ADDR and cpdmaCfg.qm1BaseAddress = QMSS_DATA_ADDR + 0x00010000, where:

//Address of remote queue manager
#define QMSS_DATA_ADDR 0x34020000

It seems that cpdmaCfg.qm0BaseAddress is set by default with QMSS_DATA_ADDR, so that's why in my first pointed example is not set.

The questions are still valid however, why you need to setup through hyperlink the QM base addresses?

The strange thing is that you set in the remote node the RXSegSel values based on a buffer address from local node. I see that the configuration is symmetric, but is this ok? If the configuration will not be symmetric how will work your example?

/Daniel

0 lding over 6 years ago in reply to Daniel Costin

TI__Guru* 95265 points

Hi,

From the "KeyStone Architecture Multicore Navigator" User's Guide, Table 4-28. Qmn Base Address Register Field Descriptions

This field programs the base address for the nth logical queue manager for the PKTDMA. Typically,
these registers point into the Queue Management region of a physical queue manager on the same
device, or a remote queue manager on another device. They must be programmed using the VBUSM
address, which is 0x34020000 for physical queue 0 (KeyStone I). The reset value for QM0 Base
Address Register defaults to this address, but QM1, QM2, and QM3 reset to 0. The most common
programming of these registers is the following:
• QM0: 0x34020000 (point to queue 0 - this is also the reset value)
• QM1: 0x34030000 (point to queue 4096)
• QM2: na
• QM3: na

So in another code you saw:

cpdmaCfg.qm0BaseAddress = QMSS_DATA_ADDR; //local QM area
cpdmaCfg.qm1BaseAddress = QMSS_DATA_ADDR + 0x00010000; //local QM area
cpdmaCfg.qm2BaseAddress = remoteQMSSPtr; //remote QM area

qm2BaseAddress address is 0x4xxx_xxxx, it is pointed to the remote side QM (0x340x_xxxx) over Hyperlink. The concept here is:

1.Setup descriptors with data inside local memory region
2.Fill in TX queues with descriptor addresses
3.Local PktDMA fetches RX free descriptor pointers from remote QMSS
4.Local PktDMA sends data to remote descriptor pointers
5.Local PktDMA sends remote descriptor pointers to remote RX queue

It is similar to how packet DMA worked inside one device, here it is extended into remote side over Hyperlink.

This example is based on using symmetric setup on TI device.

Regards, Eric

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TMS320C6678: TMS320C6678: Cppi_open initialization + memory region configurations