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Original question:

TDA4VM SOM Layout questions

TDA4VM LPDDR4 Layout questions

Tony Tsai
Prodigy 110 points


Hello,

Regarding the LPDDR4 layout impedance: in the J7221EVM design LPDDR4 of single-ended signal DQ,DM,CS,CKE using 40ohm,  CA using 33 / 66 ohm, Difference signal DQS using 80ohm, CK using 66 / 132 ohm, others using 50 ohm.

Can we follow "SPRACI2A" DDR board design and layout guidelines to use 45ohm for single-ended impedance (DQ,DM,CS,CKE,CA)? and difference signal use 85 ohm (DQS,CK)?

BR,

Tony

  • 0
    TI__Guru 52735 points

    Yes - target impedances can be adjusted based on each PCB stack-up.  Depending upon how much the impedance change, it might required different drive strength and ODT settings in the memory controller. 

    I certainly see no issue changing the singled ended data signals to 45-ohms.  With that setting, the DQS signals would likely need to target 90-ohms.  The reason the CA impedance is driven low (33-ohms) is because the T-branch needs to be 2x the single-ended.  This higher impedance can often be difficult to reach on the PCB, as the trace can get very thin.  Thus to limit - we drove the single-ended impedance very low (33-ohms) to help limit the higher impedance (66-ohms).  These values can change, but the goal is to have the T-branch impedance as close to 2x the single-ended impedance as possible. 

    SPRACI2A does not support multi-point CA signals, and does not support the same data rates as the J721E - thus it should not be followed for J721E designs.