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TMS320C6748: McASP - FIFO ordering, with multiple line in/out

Robert Wolfe
Mastermind 7860 points
Part Number: TMS320C6748
Other Parts Discussed in Thread: OMAP-L138

Hello,

I'm part of a C6748, OMAP-L138, design.  It will make use of multiple data in and out pins with a McASP.  The question is how is data structured in the McASP AFIFO, when there is data on multiple pins at the same time.  For example, on the read side, two 32 bits words could arrive on 8 data pins at the same time.  What would the contents of the RFIFO look like in that case?  For example, one scenario would be both words placed from each line, beginning on line 1, then through line 8.

AXR0, word 1

AXR0, word 2

AXR1, word 1

AXR1, word 2

.

.

.

AXR7, word 1

AXR7, word 2

Also, can you tell me what the wait state/delay is reading and writing from the AFIFO's?  Is it the same as read/write from internal memory?

Regards,

Robert

  • 0
    Mastermind 7860 points
    As clarification, I've been reminded that either the DMA RBUF can be used for the reads, or the individual RBUFs separately, i.e. RBUF0, RBUF1, etc.  Assuming we go the DMA RBUF route, it seems clear the reads will be from the lowest serializer to the highest, per these McASP/C6748 document references below:
    But how is the data read out - when more than one sample has been input to the DSP for each serializer, by the time the DSP comes back around to get all the data via the DMA RBUF reads?
    Using the simple case of 3 serializers, with 2 samples read in from each by the time the DSP does another data collection read cycle.  I envision it could be one of two scenarios, for the needed 6 sequential reads from the DMA RBUF:
    1) RBUF0 sample 1, RBUF0 sample 2, RBUF1 sample 1, RBUF1 sample 2, RBUF2 sample 1, RBUF2 sample 2
    or
    2) RBUF0 sample 1, RBUF1 sample 1, RBUF2 sample 1, RBUF0 sample 2, RBUF1 sample 2, RBUF2 sample 2
    Or maybe something else?
    Please advise,
    Robert
  • 0 in reply to Robert Wolfe
    TI__Guru*** 125430 points

    Robert Wolfe said:
    1) RBUF0 sample 1, RBUF0 sample 2, RBUF1 sample 1, RBUF1 sample 2, RBUF2 sample 1, RBUF2 sample 2

    Keep in mind that all serializers are required to use the same basic format, i.e. same number of bits per sample, etc.  Therefore all serializers will receive sample 1 simultaneously and transfer sample 1 to the FIFO.  Sample 2 will occur later in time, e.g. 32 bit clocks later.  At that time you will get a new set of samples which will be transferred to the FIFO.

    Robert Wolfe said:
    2) RBUF0 sample 1, RBUF1 sample 1, RBUF2 sample 1, RBUF0 sample 2, RBUF1 sample 2, RBUF2 sample 2

    If serializers 0, 1, 2 are active, then the FIFO contents would look like you have shown here.

  • 0 in reply to Brad Griffis
    Mastermind 7860 points

    Awesome Brad, thanks for that info.  Would you have any idea about the second question - what is the associated speed of reading from the McASP FIFO (per the DMA RBUF)?  Is it on the order of the quick reads from internal memory, or there are any delays/associated wait states?

    Robert

  • 0 in reply to Robert Wolfe
    TI__Guru*** 125430 points

    I would estimate somewhere in the neighborhood of 100-200 DSP CPU cycles.  Accordingly I recommend using EDMA to transfer from the AFIFO to DSP L2 memory.  The CPU will stall as it waits for each access to the AFIFO to be returned, but the EDMA can burst the entire read.  As a result the EDMA will be able to perform the transfer much faster than the CPU can.

  • 0 in reply to Brad Griffis
    Mastermind 7860 points

    Excellent, noted.  Thanks again.

    Robert