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Hello.
I set McASP for TX RX synchronous mode(ACLKXCTL.ASYNC bit = 0) and TDM16 mode(AFSRCTL.RMOD = 16, AFSRCTL.XMOD = 16).
I am setting the McASP according to Technical Reference Manual(SPRUH79C) section "23.0.21.1.2 Transmit/Receive Section Initialization" & "23.0.21.1.5 Synchronous Transmit and Receive Operation (ASYNC = 0)".
When Transfer is start, receiver create illegal transfer at first.
This illegal transfer equal active received serializer number.
If only SRCTL0.SRMOD = 2, illigal transfer count = 1, If SRCTL0.SRMOD and SRCTL1.SRMOD = 2, illigal transfer count = 2.
For that reason, transfer occurs in the order of "receive illegal N-transfer(N = active received serializer number)", "receive 16ch data", "receive 16ch data", ...
As a result, illegal N-transfer phase shift is occur.
This problem is receiver block only, transmitter block is not occur.
Is this behavior a specification?
Is there workaround?
Kind regards,
