SDK : ti-processor-sdk-linux-rt-am57xx-evm-06.00.00.07
Using DDR : EM6HE16EWAKG-12IH
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The board is a custom board.
I can't boot after changing the AM5718's DDR memory.
The board.c file has been modified using the EMIF RegisterConfiguration.
Is there anything else I want to change?
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emif configuration data
| /* ========================================================================= | |||
| * Copyright (C) 2017 Texas Instruments Incorporated | |||
| * | |||
| * All rights reserved. Property of Texas Instruments Incorporated. | |||
| * Restricted rights to use, duplicate or disclose this code are | |||
| * granted through contract. | |||
| * | |||
| * The program may not be used without the written permission | |||
| * of Texas Instruments Incorporated or against the terms and conditions | |||
| * stipulated in the agreement under which this program has been | |||
| * supplied. | |||
| * ========================================================================= */ | |||
| /* | |||
| * AM571x_DDR3L_666MHz_TI_AM574x_EVM_config.c | |||
| * Created on: 12/12/2019 | |||
| * Created with: EMIF_RegisterConfig_v2.0.2 | |||
| */ | |||
| #include "emif4d5_wrapper.h" | |||
| const struct dpll_params AM571x_DDR3L_666MHz_TI_AM574x_EVM_pll_params = { | |||
| .m = 333, | |||
| .n = 4, | |||
| .m2 = 2, | |||
| .m4_h11 = 8 | |||
| }; | |||
| const struct ctrl_ioregs AM571x_DDR3L_666MHz_TI_AM574x_EVM_ctrl_ioregs = { | |||
| .ctrl_ddr3ch = 0x60606060, | |||
| .ctrl_ddrch = 0x40404040, | |||
| .ctrl_ddrio_0 = 0x00094A40, | |||
| .ctrl_ddrio_1 = 0x00000000, | |||
| .ctrl_emif_sdram_config_ext = 0x0001C123 | |||
| }; | |||
| const struct dmm_lisa_map_regs AM571x_DDR3L_666MHz_TI_AM574x_EVM_dmm_regs = { | |||
| .dmm_lisa_map_0 = 0x00000000, | |||
| .dmm_lisa_map_1 = 0x00000000, | |||
| .dmm_lisa_map_2 = 0x80600100, | |||
| .dmm_lisa_map_3 = 0xFF020100, | |||
| .is_ma_present = 0x1 | |||
| }; | |||
| const struct emif_regs AM571x_DDR3L_666MHz_TI_AM574x_EVM_emif_regs = { | |||
| .sdram_config_init = 0x61862B32, | |||
| .sdram_config = 0x61862B32, | |||
| .sdram_config2 = 0x00000000, | |||
| .ref_ctrl = 0x0000514D, | |||
| .ref_ctrl_final = 0x0000144A, | |||
| .sdram_tim1 = 0xD3337834, | |||
| .sdram_tim2 = 0x30B37FE3, | |||
| .sdram_tim3 = 0x409F8AD8, | |||
| .read_idle_ctrl = 0x00050000, | |||
| .zq_config = 0x5007190B, | |||
| .temp_alert_config = 0x00000000, | |||
| .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | |||
| .emif_rd_wr_lvl_ctl = 0x00000000, | |||
| .emif_ddr_phy_ctlr_1_init = 0x0824400E, | |||
| .emif_ddr_phy_ctlr_1 = 0x0E24400E, | |||
| .emif_rd_wr_exec_thresh = 0x00000305, | |||
| .emif_ecc_ctrl_reg = 0xC0000001, | |||
| .emif_ecc_address_range_1 = 0x3FFF0000, | |||
| .emif_ecc_address_range_2 = 0x00000000, | |||
| }; | |||
| /* | |||
| * DLL Ratio Values are an estimate based on trace lengths. Either | |||
| * software leveling or hardware leveling should be performed to | |||
| * determine final DLL values. | |||
| */ | |||
| const unsigned int AM571x_DDR3L_666MHz_TI_AM574x_EVM_emif1_ext_phy_regs [] = { | |||
| 0x04040100, | // EMIF1_EXT_PHY_CTRL_1 | ||
| 0x006B006B, | // EMIF1_EXT_PHY_CTRL_2 | ||
| 0x006B006B, | // EMIF1_EXT_PHY_CTRL_3 | ||
| 0x006B006B, | // EMIF1_EXT_PHY_CTRL_4 | ||
| 0x006B006B, | // EMIF1_EXT_PHY_CTRL_5 | ||
| 0x006B006B, | // EMIF1_EXT_PHY_CTRL_6 | ||
| 0x002F002F, | // EMIF1_EXT_PHY_CTRL_7 | ||
| 0x002F002F, | // EMIF1_EXT_PHY_CTRL_8 | ||
| 0x002F002F, | // EMIF1_EXT_PHY_CTRL_9 | ||
| 0x002F002F, | // EMIF1_EXT_PHY_CTRL_10 | ||
| 0x002F002F, | // EMIF1_EXT_PHY_CTRL_11 | ||
| 0x00600060, | // EMIF1_EXT_PHY_CTRL_12 | ||
| 0x00600060, | // EMIF1_EXT_PHY_CTRL_13 | ||
| 0x00600060, | // EMIF1_EXT_PHY_CTRL_14 | ||
| 0x00600060, | // EMIF1_EXT_PHY_CTRL_15 | ||
| 0x00600060, | // EMIF1_EXT_PHY_CTRL_16 | ||
| 0x00400040, | // EMIF1_EXT_PHY_CTRL_17 | ||
| 0x00400040, | // EMIF1_EXT_PHY_CTRL_18 | ||
| 0x00400040, | // EMIF1_EXT_PHY_CTRL_19 | ||
| 0x00400040, | // EMIF1_EXT_PHY_CTRL_20 | ||
| 0x00400040, | // EMIF1_EXT_PHY_CTRL_21 | ||
| 0x00800080, | // EMIF1_EXT_PHY_CTRL_22 | ||
| 0x00800080, | // EMIF1_EXT_PHY_CTRL_23 | ||
| 0x40010080, | // EMIF1_EXT_PHY_CTRL_24 | ||
| 0x08102040, | // EMIF1_EXT_PHY_CTRL_25 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_26 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_27 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_28 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_29 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_30 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_31 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_32 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_33 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_34 | ||
| 0x00000000, | // EMIF1_EXT_PHY_CTRL_35 | ||
| 0x00000077 | // EMIF1_EXT_PHY_CTRL_36 | ||
| }; | |||
| struct emif_cfg AM571x_DDR3L_666MHz_TI_AM574x_EVM = { | |||
| .platform = "AM571x_DDR3L_666MHz_TI_AM574x_EVM", | |||
| .EMIF2_DEFINED = 0, | |||
| .pll_regs = &AM571x_DDR3L_666MHz_TI_AM574x_EVM_pll_params, | |||
| .ctrl_regs = &AM571x_DDR3L_666MHz_TI_AM574x_EVM_ctrl_ioregs, | |||
| .dmm_regs = &AM571x_DDR3L_666MHz_TI_AM574x_EVM_dmm_regs, | |||
| .regs = &AM571x_DDR3L_666MHz_TI_AM574x_EVM_emif_regs, | |||
| .phy_regs1 = AM571x_DDR3L_666MHz_TI_AM574x_EVM_emif1_ext_phy_regs, | |||
| }; |
