TDA2PXEVM: Provide frames from CSI(CAL) to VIP on the fly

Vladimir Yakovlev1

Part Number: TDA2PXEVM

How I can configure vsdk links for provide frames for 4x channels from ISS to VIP on the fly? Or maybe have you example for vps drivers? It's need for convert 422I to 420SP without access to DDR and save bandwith DDR from excess RD/WR

as in the example 2.1.4 CAL to VIP 4 Channel Capture (SPRACE3A–April 2018)

over 5 years ago

0 Sujith over 5 years ago

TI__Genius 12455 points

Hi Valdimir,

This is supported on TDA2Px but i am not sure if the driver and/or link support the same.

Let me check on this and come back to you in the first week of Jan 2020

Regards, Sujith

0 Sujith over 5 years ago in reply to Sujith

TI__Genius 12455 points

Hi Valdimir,

This is not supported in the driver or the link of VisionSDK. But supported in the hardware.

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Hello, Sujith!

Thank you for your reply.

Could you say.

Does TI has plan to implement this functionality in future releases of VSDK?

Or maybe are you have example of configuration this functionality in PDK?

0 Sujith over 5 years ago in reply to Vladimir Yakovlev1

TI__Genius 12455 points

Hi Valdimir,

This is not scheduled to be implemented. I will have to check on the reference code.

Regards, Sujith

0 Sujith over 5 years ago in reply to Sujith

TI__Genius 12455 points

Hi Valdimir,

Is your question answered? If so, please mark the thread as answered. If you more questions, please post new query.

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Hello, Sujith!

I wait answer for second part of my question:

>Or maybe are you have example of configuration this functionality in PDK?

or other lower layer sample code

0 Sujith over 5 years ago in reply to Vladimir Yakovlev1

TI__Genius 12455 points

Hi Valdimir,

I will try and locate the required configuration. Since, the link/driver do not support this mode, you would require to update the driver and Link to support this feature.

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Hello, Sujith!

Yes of course. It will requere update driver and Link. It's no problem. But need example code with steps how to configure HW.

Thanks!

BR, Vladimir

0 Sujith over 5 years ago in reply to Vladimir Yakovlev1

TI__Genius 12455 points

Hi Vladmir,

Sorry for the delayed response, i could finally locate the test code. Can you please below listed changes

1. Make the CAL not write the received streams into memory

1.1. Link would require an update

1.2. In function IssCaptureLink_drvSetDrvCfg () in file vision_sdk\links_fw\src\rtos\links_ipu\iss_capture\issCaptureLink_drv.c

1.2.1. set drvCalCfg->writeToMem[strmId] = (UInt32)FALSE;

1.2.2. Assuming other aspects of CAL are setup to receive 4 channels of video stream

2. Configure the VPORT to send out the received data

2.1. In function IssCaptureLink_drvSetDrvCfg () in file vision_sdk\links_fw\src\rtos\links_ipu\iss_capture\issCaptureLink_drv.c

2.2. drvCalCfg->isVportCfgValid[strmId] = (UInt32)TRUE;

drvCalCfg->vportCfg[0U].enable = TRUE;

drvCalCfg->vportCfg[0U].pixClock = 20480U;

drvCalCfg->vportCfg[0U].width = 0U;

drvCalCfg->vportCfg[0U].xBlk = 0x4U;

drvCalCfg->vportCfg[0U].yBlk = 0x3CU;

drvCalCfg->vportCfg[0U].rdyThr = 0U;

drvCalCfg->vportCfg[0U].fsReset = TRUE;

2.4. Update Driver to send via vPort

In file \ti_components\drivers\pdk\packages\ti\drv\vps\src\vpslib\hal\src\vpshal_isscal.c

In function CalSetVportCfg ()

{

/* Before VPORT register is written i.e.

Before HW_WR_REG32(baseAddr + CAL_VPORT_CTRL2, reg); */

/* Enable transmission on vports 2, 3 & 4 */

reg = reg | 0x20U;

/* Configure the cport ID's */

reg = reg | 0x01U'

HW_WR_REG32(baseAddr + CAL_VPORT_CTRL2, reg);

}

2.5. Update the config to route CAL output to VIP

Un Lock MMR access to control register

i.e. Write to value 0xE2BC3A6D to register CTRL_CORE_MMR_LOCK_3

Select inputs to VIP

i.e. Register CTRL_CORE_CONTROL_SPARE_RW, set bits VIP_SEL_4A, VIP_SEL_3A, VIP_SEL_2A & VIP_SEL_1A

3. Configure VIP normally for 16 bit discrete sync mode reception

Sync Signals are active high

4. Start VIP

5. Start CAL

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Hello, Sujith!

Thanks for your reply. I will check it and return for close the thread or for new questions

And also small quastion: In step 2.5 I must call PlatformUnlockMMR(). Do I must call PlatformLockMMR() for apply new params

BR, Vladimir

0 Sujith over 5 years ago in reply to Vladimir Yakovlev1

TI__Genius 12455 points

Hi Vladmir,

Ideally should call lock after programming the MMR.

Regards, Sujith

0 Sujith over 5 years ago in reply to Sujith

TI__Genius 12455 points

Hi Vladmir,

Did you get a chance to check on the steps provided? If you require mote time to check on this, suggest to close this thread and start a new one when you have more questions.

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Hello Sujith,

Sorry for the late reply.

I reproduced all as in your steps but my pipeline does not get new frames from VIP. I think it's because incorrectly configured pixClock in vportCfg. I will check it.

drvCalCfg->isVportCfgValid[strmId] = (UInt32)TRUE;

drvCalCfg->vportCfg[strmId].enable = (UInt32)TRUE;
drvCalCfg->vportCfg[strmId].pixClock = 20480U;

I also noticed what VIP2 has transaction data to DDR after start time and has not transaction after any time

[IPU1-0] 34.355822 s: SCI_VIP2_P1 | 0.000000 0.000000
[IPU1-0] 34.355914 s: SCI_VIP2_P2 | 0.000051 0.058671
..
[IPU1-0] 155.776733 s: SCI_VIP2_P1 | 0.000000 0.000000
[IPU1-0] 155.776855 s: SCI_VIP2_P2 | 0.000000 0.000000

I attached file with changes and config, and file with logs. Could you check my config?

cal2vip_log.txt

Fullscreen

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[IPU1-0]     23.939943 s: Start DONE!
[IPU1-0]  
[IPU1-0]  ====================
[IPU1-0]  Chains Run-time Menu
[IPU1-0]  ====================
[IPU1-0]  
[IPU1-0]  q: Stop Chain
[IPU1-0]  d: Save ISS Captured Frame
[IPU1-0]  r: Switch Mosaic 4xCam Disp <-> Rear view Disp
[IPU1-0]  
[IPU1-0]  p: Print Performance Statistics 
[IPU1-0]  
[IPU1-0]  +: Increase display brightness
[IPU1-0]  
[IPU1-0]  -: Decrease display brightness
[IPU1-0]  
[IPU1-0]  Enter Choice: 
[IPU1-0]  
[IPU1-0]     33.330750 s: arrival_pipeline_printBufferStatistics Start ...
[IPU1-0]     33.330903 s:  [ISSCAPTURE] Buffer Q Status,
[IPU1-0]     33.330994 s:  Empty Q : Elements in Q =   0, Write Idx =   0, Read Idx =   0
[IPU1-0]     33.331116 s:  Full  Q : Elements in Q =   6, Write Idx =   6, Read Idx =   0
[IPU1-0]     33.331330 s:  [CAPTURE] Buffer Q Status,
[IPU1-0]     33.331391 s:  Empty Q : Elements in Q =   0, Write Idx =   0, Read Idx =   0
[IPU1-0]     33.331482 s:  Full  Q : Elements in Q =   0, Write Idx =   0, Read Idx =   0
[IPU1-0]     33.331879 s: arrival_pipeline_printBufferStatistics End ...
[IPU1-0]     33.331970 s: arrival_pipeline_printStatistics Start ...
[IPU1-0]     33.332153 s:  
[IPU1-0]     33.332184 s:  ### CPU [IPU1-0], LinkID [ 87],
[IPU1-0]     33.332275 s:  
[IPU1-0]     33.332306 s:  [ ISSCAPTURE ] Link Statistics,
...
...
...
[IPU1-0]     33.332397 s:  ******************************
[IPU1-0]     33.332458 s:  
[IPU1-0]     33.332489 s:  Elapsed time       = 15587 msec
[IPU1-0]     33.332550 s:  
[IPU1-0]     33.332611 s:  Driver/Notify Cb   =   2.56 fps
[IPU1-0]     33.332672 s:  
[IPU1-0]     33.332733 s:  Input Statistics,
[IPU1-0]     33.332763 s:  
[IPU1-0]     33.332824 s:  CH | In Recv | In Drop | In User Drop | In Process 
[IPU1-0]     33.332885 s:     | FPS     | FPS     | FPS          | FPS        
[IPU1-0]     33.332977 s:  -------------------------------------------------- 
[IPU1-0]     33.333099 s:  
[IPU1-0]     33.333129 s:  Output Statistics,
[IPU1-0]     33.333190 s:  
[IPU1-0]     33.333221 s:  CH | Out | Out     | Out Drop | Out User Drop 
[IPU1-0]     33.333312 s:     | ID  | FPS     | FPS      | FPS           
[IPU1-0]     33.333374 s:  --------------------------------------------- 
[IPU1-0]     33.333465 s:   4 |  0      0.19     0. 0      0. 0 
[IPU1-0]     33.333587 s:   5 |  0      0.19     0. 0      0. 0 
[IPU1-0]     33.333709 s:  
[IPU1-0]     33.333740 s:  [ ISSCAPTURE ] LATENCY,
[IPU1-0]     33.333801 s:  ********************
[IPU1-0]     33.333862 s:  
[IPU1-0]     33.333984 s:  
[IPU1-0]     33.334289 s:  ### CPU [IPU1-0], LinkID [ 74],
[IPU1-0]     33.334380 s:  
[IPU1-0]     33.334411 s:  [ CAPTURE ] Link Statistics,
[IPU1-0]     33.334472 s:  ******************************
[IPU1-0]     33.334533 s:  
[IPU1-0]     33.334594 s:  Elapsed time       = 15731 msec
[IPU1-0]     33.334655 s:  
[IPU1-0]     33.334685 s:  
[IPU1-0]     33.334746 s:  Input Statistics,
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

[IPU1-0]     23.939943 s: Start DONE!
[IPU1-0]  
[IPU1-0]  ====================
[IPU1-0]  Chains Run-time Menu
[IPU1-0]  ====================
[IPU1-0]  
[IPU1-0]  q: Stop Chain
[IPU1-0]  d: Save ISS Captured Frame
[IPU1-0]  r: Switch Mosaic 4xCam Disp <-> Rear view Disp
[IPU1-0]  
[IPU1-0]  p: Print Performance Statistics 
[IPU1-0]  
[IPU1-0]  +: Increase display brightness
[IPU1-0]  
[IPU1-0]  -: Decrease display brightness
[IPU1-0]  
[IPU1-0]  Enter Choice: 
[IPU1-0]  
[IPU1-0]     33.330750 s: arrival_pipeline_printBufferStatistics Start ...
[IPU1-0]     33.330903 s:  [ISSCAPTURE] Buffer Q Status,
[IPU1-0]     33.330994 s:  Empty Q : Elements in Q =   0, Write Idx =   0, Read Idx =   0
[IPU1-0]     33.331116 s:  Full  Q : Elements in Q =   6, Write Idx =   6, Read Idx =   0
[IPU1-0]     33.331330 s:  [CAPTURE] Buffer Q Status,
[IPU1-0]     33.331391 s:  Empty Q : Elements in Q =   0, Write Idx =   0, Read Idx =   0
[IPU1-0]     33.331482 s:  Full  Q : Elements in Q =   0, Write Idx =   0, Read Idx =   0
[IPU1-0]     33.331879 s: arrival_pipeline_printBufferStatistics End ...
[IPU1-0]     33.331970 s: arrival_pipeline_printStatistics Start ...
[IPU1-0]     33.332153 s:  
[IPU1-0]     33.332184 s:  ### CPU [IPU1-0], LinkID [ 87],
[IPU1-0]     33.332275 s:  
[IPU1-0]     33.332306 s:  [ ISSCAPTURE ] Link Statistics,
...
...
...
[IPU1-0]     33.332397 s:  ******************************
[IPU1-0]     33.332458 s:  
[IPU1-0]     33.332489 s:  Elapsed time       = 15587 msec
[IPU1-0]     33.332550 s:  
[IPU1-0]     33.332611 s:  Driver/Notify Cb   =   2.56 fps
[IPU1-0]     33.332672 s:  
[IPU1-0]     33.332733 s:  Input Statistics,
[IPU1-0]     33.332763 s:  
[IPU1-0]     33.332824 s:  CH | In Recv | In Drop | In User Drop | In Process 
[IPU1-0]     33.332885 s:     | FPS     | FPS     | FPS          | FPS        
[IPU1-0]     33.332977 s:  -------------------------------------------------- 
[IPU1-0]     33.333099 s:  
[IPU1-0]     33.333129 s:  Output Statistics,
[IPU1-0]     33.333190 s:  
[IPU1-0]     33.333221 s:  CH | Out | Out     | Out Drop | Out User Drop 
[IPU1-0]     33.333312 s:     | ID  | FPS     | FPS      | FPS           
[IPU1-0]     33.333374 s:  --------------------------------------------- 
[IPU1-0]     33.333465 s:   4 |  0      0.19     0. 0      0. 0 
[IPU1-0]     33.333587 s:   5 |  0      0.19     0. 0      0. 0 
[IPU1-0]     33.333709 s:  
[IPU1-0]     33.333740 s:  [ ISSCAPTURE ] LATENCY,
[IPU1-0]     33.333801 s:  ********************
[IPU1-0]     33.333862 s:  
[IPU1-0]     33.333984 s:  
[IPU1-0]     33.334289 s:  ### CPU [IPU1-0], LinkID [ 74],
[IPU1-0]     33.334380 s:  
[IPU1-0]     33.334411 s:  [ CAPTURE ] Link Statistics,
[IPU1-0]     33.334472 s:  ******************************
[IPU1-0]     33.334533 s:  
[IPU1-0]     33.334594 s:  Elapsed time       = 15731 msec
[IPU1-0]     33.334655 s:  
[IPU1-0]     33.334685 s:  
[IPU1-0]     33.334746 s:  Input Statistics,
[IPU1-0]     33.334777 s:  
[IPU1-0]     33.334838 s:  CH | In Recv | In Drop | In User Drop | In Process 
[IPU1-0]     33.334899 s:     | FPS     | FPS     | FPS          | FPS        
[IPU1-0]     33.334990 s:  -------------------------------------------------- 
[IPU1-0]     33.335112 s:  
[IPU1-0]     33.335143 s:  Output Statistics,
[IPU1-0]     33.335204 s:  
[IPU1-0]     33.335234 s:  CH | Out | Out     | Out Drop | Out User Drop 
[IPU1-0]     33.335326 s:     | ID  | FPS     | FPS      | FPS           
[IPU1-0]     33.335387 s:  --------------------------------------------- 
[IPU1-0]     33.335478 s:  
[IPU1-0]     33.335539 s:  [ CAPTURE ] LATENCY,
[IPU1-0]     33.335600 s:  ********************
[IPU1-0]     33.335661 s:  
...
...
...
[IPU1-0]     34.352223 s:  Statistics Collector,
[IPU1-0]     34.352284 s:  
[IPU1-0]     34.352345 s:        STATISTIC          Avg Data        Peak Data 
[IPU1-0]     34.352406 s:        COLLECTOR          MB/s            MB/s      
[IPU1-0]     34.352498 s:  -------------------------------------------------- 
[IPU1-0]     34.352589 s:  SCI_EMIF1 RD+WR      |    103.968940    307.064374
[IPU1-0]     34.352681 s:  SCI_EMIF2 RD+WR      |    164.467865    362.024790
[IPU1-0]     34.352803 s:  SCI_EMIF1 RD ONLY    |     78.796397    110.901201
[IPU1-0]     34.352925 s:  SCI_EMIF1 WR ONLY    |     25.211151    235.041983
[IPU1-0]     34.353047 s:  SCI_EMIF2 RD ONLY    |     86.652204    118.403644
[IPU1-0]     34.353169 s:  SCI_EMIF2 WR ONLY    |     77.908386    283.006797
[IPU1-0]     34.353291 s:  SCI_MA_MPU_P1        |      0.076559      1.311475
[IPU1-0]     34.353382 s:  SCI_MA_MPU_P2        |      0.001521      1.156441
[IPU1-0]     34.353504 s:  SCI_DSS              |      0.000000      0.000000
[IPU1-0]     34.353596 s:  SCI_IPU1             |      9.994995     36.882352
[IPU1-0]     34.353718 s:  SCI_VIP1_P1          |      0.000000      0.000000
[IPU1-0]     34.353809 s:  SCI_VIP1_P2          |      0.000000      0.000000
[IPU1-0]     34.353901 s:  SCI_VPE_P1           |      0.000000      0.000000
[IPU1-0]     34.354023 s:  SCI_VPE_P2           |      0.000000      0.000000
[IPU1-0]     34.354389 s:  SCI_DSP1_MDMA        |      6.335870      7.499497
[IPU1-0]     34.354511 s:  SCI_DSP1_EDMA        |      0.000000      0.000000
[IPU1-0]     34.354633 s:  SCI_DSP2_MDMA        |      6.338431      7.502715
[IPU1-0]     34.354724 s:  SCI_DSP2_EDMA        |      0.000000      0.000000
[IPU1-0]     34.354816 s:  SCI_EVE1_TC0         |     25.098654     26.123516
[IPU1-0]     34.354938 s:  SCI_EVE1_TC1         |      0.000000      0.000000
[IPU1-0]     34.355060 s:  SCI_EVE2_TC0         |     25.099605     26.059533
[IPU1-0]     34.355182 s:  SCI_EVE2_TC1         |      0.000000      0.000000
[IPU1-0]     34.355304 s:  SCI_EDMA_TC0_RD      |      0.000000      0.000000
[IPU1-0]     34.355395 s:  SCI_EDMA_TC0_WR      |      0.000000      0.000000
[IPU1-0]     34.355487 s:  SCI_EDMA_TC1_RD      |      0.000000      0.000000
[IPU1-0]     34.355609 s:  SCI_EDMA_TC1_WR      |      0.000000      0.000000
[IPU1-0]     34.355822 s:  SCI_VIP2_P1          |      0.000000      0.000000
[IPU1-0]     34.355914 s:  SCI_VIP2_P2          |      0.000051      0.058671
[IPU1-0]     34.356066 s:  SCI_IVA              |      0.000000      0.000000
[IPU1-0]     34.356188 s:  SCI_GPU_P1           |      0.000000      0.000000
[IPU1-0]     34.356280 s:  SCI_GPU_P2           |      0.000000      0.000000
[IPU1-0]     34.356371 s:  SCI_GMAC_SW          |      0.000000      0.000000
[IPU1-0]     34.356493 s:  SCI_OCMC_RAM1        |      0.000000      0.000000
[IPU1-0]     34.356585 s:  SCI_OCMC_RAM2        |      0.000000      0.000000
[IPU1-0]     34.356676 s:  SCI_OCMC_RAM3        |      0.000000      0.000000
[IPU1-0]     34.356798 s:  SCI_ISS_RT           |      0.000000      0.000000
[IPU1-0]     34.356890 s:  SCI_ISS_NRT1         |      0.000000      0.000000
[IPU1-0]     34.357012 s:  SCI_ISS_NRT2         |      0.000000      0.000000
[IPU1-0]     34.357134 s:  SCI_CAL              |     10.875226    443.822471
...
...
...
[IPU1-0]    155.773500 s:  Statistics Collector,
[IPU1-0]    155.773561 s:  
[IPU1-0]    155.773622 s:        STATISTIC          Avg Data        Peak Data 
[IPU1-0]    155.773683 s:        COLLECTOR          MB/s            MB/s      
[IPU1-0]    155.773775 s:  -------------------------------------------------- 
[IPU1-0]    155.773866 s:  SCI_EMIF1 RD+WR      |     82.064484     94.340552
[IPU1-0]    155.773988 s:  SCI_EMIF2 RD+WR      |    143.028894    154.354063
[IPU1-0]    155.774080 s:  SCI_EMIF1 RD ONLY    |     69.808298     76.306216
[IPU1-0]    155.774202 s:  SCI_EMIF1 WR ONLY    |     12.288926     18.174448
[IPU1-0]    155.774324 s:  SCI_EMIF2 RD ONLY    |     77.795830     83.544605
[IPU1-0]    155.774446 s:  SCI_EMIF2 WR ONLY    |     65.362875     70.930260
[IPU1-0]    155.774568 s:  SCI_MA_MPU_P1        |      0.069448      1.250699
[IPU1-0]    155.774690 s:  SCI_MA_MPU_P2        |      0.000569      1.010795
[IPU1-0]    155.774781 s:  SCI_DSS              |      0.000000      0.000000
[IPU1-0]    155.774903 s:  SCI_IPU1             |      6.306200     20.779654
[IPU1-0]    155.774995 s:  SCI_VIP1_P1          |      0.000000      0.000000
[IPU1-0]    155.775086 s:  SCI_VIP1_P2          |      0.000000      0.000000
[IPU1-0]    155.775208 s:  SCI_VPE_P1           |      0.000000      0.000000
[IPU1-0]    155.775330 s:  SCI_VPE_P2           |      0.000000      0.000000
[IPU1-0]    155.775452 s:  SCI_DSP1_MDMA        |      6.337710      8.078037
[IPU1-0]    155.775544 s:  SCI_DSP1_EDMA        |      0.000000      0.000000
[IPU1-0]    155.775666 s:  SCI_DSP2_MDMA        |      6.339945      8.045581
[IPU1-0]    155.775757 s:  SCI_DSP2_EDMA        |      0.000000      0.000000
[IPU1-0]    155.775879 s:  SCI_EVE1_TC0         |     25.117463     26.056315
[IPU1-0]    155.775971 s:  SCI_EVE1_TC1         |      0.000000      0.000000
[IPU1-0]    155.776093 s:  SCI_EVE2_TC0         |     25.117316     26.099376
[IPU1-0]    155.776184 s:  SCI_EVE2_TC1         |      0.000000      0.000000
[IPU1-0]    155.776306 s:  SCI_EDMA_TC0_RD      |      0.000000      0.000000
[IPU1-0]    155.776428 s:  SCI_EDMA_TC0_WR      |      0.000000      0.000000
[IPU1-0]    155.776550 s:  SCI_EDMA_TC1_RD      |      0.000000      0.000000
[IPU1-0]    155.776642 s:  SCI_EDMA_TC1_WR      |      0.000000      0.000000
[IPU1-0]    155.776733 s:  SCI_VIP2_P1          |      0.000000      0.000000
[IPU1-0]    155.776855 s:  SCI_VIP2_P2          |      0.000000      0.000000
[IPU1-0]    155.777069 s:  SCI_IVA              |      0.000000      0.000000
[IPU1-0]    155.777160 s:  SCI_GPU_P1           |      0.000000      0.000000
[IPU1-0]    155.777282 s:  SCI_GPU_P2           |      0.000000      0.000000
[IPU1-0]    155.777587 s:  SCI_GMAC_SW          |      0.000000      0.000000
[IPU1-0]    155.777709 s:  SCI_OCMC_RAM1        |      0.000000      0.000000
[IPU1-0]    155.777832 s:  SCI_OCMC_RAM2        |      0.000000      0.000000
[IPU1-0]    155.777923 s:  SCI_OCMC_RAM3        |      0.000000      0.000000
[IPU1-0]    155.778015 s:  SCI_ISS_RT           |      0.000000      0.000000
[IPU1-0]    155.778137 s:  SCI_ISS_NRT1         |      0.000000      0.000000
[IPU1-0]    155.778228 s:  SCI_ISS_NRT2         |      0.000000      0.000000
[IPU1-0]    155.778381 s:  SCI_CAL              |      0.000000      0.000000
[IPU1-0]    155.878332 s: FPDLink_camera_print_status Start ...
[IPU1-0]    155.878454 s: ##################################################
[IPU1-0]    155.878515 s: ########## Check status for CSI port 0 ##########
[IPU1-0]    155.878606 s: ##################################################
[IPU1-0]    155.879338 s: UB960: Forwarding is not synchronized for CSI-2 output port 1 
[IPU1-0]    155.879460 s: UB960: Forwarding is not synchronized for CSI-2 output port 0 
[IPU1-0]    155.882510 s: UB960: CSI0_FRAME_COUNT = 8153 
[IPU1-0]    155.884340 s: UB960: CSI0_FRAME_ERR_COUNT = 0 
[IPU1-0]    155.886353 s: UB960: CSI0_LINE_COUNT =  65535 
[IPU1-0]    155.888336 s: UB960: CSI0_LINE_ERR_COUNT = 0 
[IPU1-0]    155.889343 s: Check status for RX chan 0: 
[IPU1-0]    155.892515 s: UB960_RX0: RX_PORT_NUM = RX0 
[IPU1-0]    155.892606 s: UB960_RX0: PORT_PASS=1 
[IPU1-0]    155.892667 s: UB960_RX0: LOCK_STS=1 
[IPU1-0]    155.893338 s: UB960_RX0: FREQ_STABLE DETECTED 
[IPU1-0]    155.895351 s: UB960_RX0: Line count 1080 
[IPU1-0]    155.897517 s: UB960_RX0: Line Length 3840 
[IPU1-0]    155.898462 s: UB960_RX0: CSI_RX_STS 0x00 
[IPU1-0]    155.899347 s: UB960_RX0: CSI_ERR_COUNTER 0 
[IPU1-0]    155.900414 s:   UB953:Device STS = 0xC0 
[IPU1-0]    155.901329 s:   UB953:GENERAL_STATUS = 0x45 
[IPU1-0]    155.901421 s:    LINE_LEN_CHG 
[IPU1-0]    155.901482 s:    FREQ_STABLE DETECTED 
[IPU1-0]    155.901543 s:    LINE_CNT_CHG DETECTED 
[IPU1-0]    155.902519 s:   UB953:GPIO_PIN_STS = 0x04 
[IPU1-0]    155.903342 s:   UB953:BIST_ERR_CNT = 0x00 
[IPU1-0]    155.904349 s:   UB953:CRC_ERR_CNT1 = 0x00 
[IPU1-0]    155.905355 s:   UB953:CRC_ERR_CNT2 = 0x00 
[IPU1-0]    155.906331 s:   UB953:CSI_ERR_CNT = 0x00 
[IPU1-0]    155.907521 s:   UB953:CSI_ERR_STATUS = 0x00 
[IPU1-0]    155.908345 s:   UB953:CSI_ERR_DLANE01 = 0x00 
[IPU1-0]    155.909351 s:   UB953:CSI_ERR_DLANE23 = 0x00 
[IPU1-0]    155.910419 s:   UB953:CSI_ERR_CLK_LANE = 0x00 
[IPU1-0]    155.911334 s:   UB953:CSI_PKT_HDR_VC_ID = 0x1E 
[IPU1-0]    155.912523 s:   UB953:PKT_HDR_WC_LSB = 0x00 
[IPU1-0]    155.913347 s:   UB953:PKT_HDR_WC_MSB = 0x0F 
[IPU1-0]    155.914353 s:   UB953: CSI_ECC = 0x14 
[IPU1-0]    155.923351 s: RDACM51: STV0971 device ID = 0x000003CB 
[IPU1-0]    155.932532 s: RDACM51: STV0971 cut number = 0x00000010 
[IPU1-0]    155.942505 s: RDACM51: Engineering tracking number = 0x00000000 
[IPU1-0]    155.952510 s: RDACM51: STV0971 firmware revision = 0x00000208 
[IPU1-0]    155.961324 s: RDACM51: STV0971 firmware patch revision = 0x0000000F 
[IPU1-0]    155.970353 s: RDACM51: STV0971 firmware UI revision = 0x00000067 
[IPU1-0]    155.979320 s: RDACM51: FSM_MODE = 0x00000004 
[IPU1-0]    155.988348 s: RDACM51: CMD_HOLD_STATE = 0x00000000 
[IPU1-0]    155.997529 s: RDACM51: SAFETY_STATUS= 0x00000000 
[IPU1-0]    156.006344 s: RDACM51: SAFETY_DURATION_USEC = 0x00000000 
[IPU1-0]    156.015341 s: RDACM51: INTER_FRAME_USEC = 0x00009A97 
[IPU1-0]    156.024339 s: RDACM51: TEMPERATURE = 0x0000003B 
[IPU1-0]    156.033337 s: RDACM51: FRAME_COUNTER = 0x000007BD 
[IPU1-0]    156.042487 s: RDACM51: FRAME_CORRUPTED = 0x00000000 
[IPU1-0]    156.052522 s: RDACM51: FRAME_LENGTH = 0x00000A6B 
[IPU1-0]    156.061337 s: RDACM51: LINE_LENGTH = 0x000009C4 
[IPU1-0]    156.070365 s: RDACM51: X_ADDR_START = 0x00000000 
[IPU1-0]    156.079332 s: RDACM51: Y_ADDR_START = 0x00000000 
[IPU1-0]    156.088360 s: RDACM51: X_OUTPUT_SIZE = 0x00000780 
[IPU1-0]    156.097511 s: RDACM51: Y_OUTPUT_SIZE = 0x00000438 
[IPU1-0]    156.106356 s: RDACM51: STATUS_LINE_DATA = 0x00000000 
[IPU1-0]    156.107515 s: Check status for RX chan 1: 
[IPU1-0]    156.110351 s: UB960_RX1: RX_PORT_NUM = RX1 
[IPU1-0]    156.110443 s: UB960_RX1: PORT_PASS=1 
[IPU1-0]    156.110504 s: UB960_RX1: LOCK_STS=1 
[IPU1-0]    156.111419 s: UB960_RX1: FREQ_STABLE DETECTED 
[IPU1-0]    156.113371 s: UB960_RX1: Line count 1080 
[IPU1-0]    156.115476 s: UB960_RX1: Line Length 3840 
[IPU1-0]    156.116360 s: UB960_RX1: CSI_RX_STS 0x00 
[IPU1-0]    156.117519 s: UB960_RX1: CSI_ERR_COUNTER 0 
[IPU1-0]    156.118343 s:   UB953:Device STS = 0xC0 
[IPU1-0]    156.119349 s:   UB953:GENERAL_STATUS = 0x45 
[IPU1-0]    156.119441 s:    LINE_LEN_CHG 
[IPU1-0]    156.119471 s:    FREQ_STABLE DETECTED 
[IPU1-0]    156.119532 s:    LINE_CNT_CHG DETECTED 
[IPU1-0]    156.120356 s:   UB953:GPIO_PIN_STS = 0x04 
[IPU1-0]    156.121332 s:   UB953:BIST_ERR_CNT = 0x00 
[IPU1-0]    156.122521 s:   UB953:CRC_ERR_CNT1 = 0x00 
[IPU1-0]    156.123345 s:   UB953:CRC_ERR_CNT2 = 0x00 
[IPU1-0]    156.124412 s:   UB953:CSI_ERR_CNT = 0x00 
[IPU1-0]    156.125358 s:   UB953:CSI_ERR_STATUS = 0x00 
[IPU1-0]    156.126334 s:   UB953:CSI_ERR_DLANE01 = 0x00 
[IPU1-0]    156.127523 s:   UB953:CSI_ERR_DLANE23 = 0x00 
[IPU1-0]    156.128347 s:   UB953:CSI_ERR_CLK_LANE = 0x00 
[IPU1-0]    156.129414 s:   UB953:CSI_PKT_HDR_VC_ID = 0x1E 
[IPU1-0]    156.130360 s:   UB953:PKT_HDR_WC_LSB = 0x00 
[IPU1-0]    156.131336 s:   UB953:PKT_HDR_WC_MSB = 0x0F 
[IPU1-0]    156.132526 s:   UB953: CSI_ECC = 0x14 
[IPU1-0]    156.141340 s: RDACM51: STV0971 device ID = 0x000003CB 
[IPU1-0]    156.151406 s: RDACM51: STV0971 cut number = 0x00000010 
[IPU1-0]    156.162508 s: RDACM51: Engineering tracking number = 0x00000000 
[IPU1-0]    156.171353 s: RDACM51: STV0971 firmware revision = 0x00000208 
[IPU1-0]    156.180351 s: RDACM51: STV0971 firmware patch revision = 0x0000000F 
[IPU1-0]    156.189349 s: RDACM51: STV0971 firmware UI revision = 0x00000067 
[IPU1-0]    156.198346 s: RDACM51: FSM_MODE = 0x00000004 
[IPU1-0]    156.207527 s: RDACM51: CMD_HOLD_STATE = 0x00000000 
[IPU1-0]    156.216342 s: RDACM51: SAFETY_STATUS= 0x00000000 
[IPU1-0]    156.225340 s: RDACM51: SAFETY_DURATION_USEC = 0x00000000 
[IPU1-0]    156.234368 s: RDACM51: INTER_FRAME_USEC = 0x00009A97 
[IPU1-0]    156.243366 s: RDACM51: TEMPERATURE = 0x00000036 
[IPU1-0]    156.252516 s: RDACM51: FRAME_COUNTER = 0x000007C0 
[IPU1-0]    156.261331 s: RDACM51: FRAME_CORRUPTED = 0x00000000 
[IPU1-0]    156.271335 s: RDACM51: FRAME_LENGTH = 0x00000A6B 
[IPU1-0]    156.281339 s: RDACM51: LINE_LENGTH = 0x000009C4 
[IPU1-0]    156.290337 s: RDACM51: X_ADDR_START = 0x00000000 
[IPU1-0]    156.299335 s: RDACM51: Y_ADDR_START = 0x00000000 
[IPU1-0]    156.308363 s: RDACM51: X_OUTPUT_SIZE = 0x00000780 
[IPU1-0]    156.317513 s: RDACM51: Y_OUTPUT_SIZE = 0x00000438 
[IPU1-0]    156.326358 s: RDACM51: STATUS_LINE_DATA = 0x00000000 
[IPU1-0]    156.327517 s: Check status for RX chan 2: 
[IPU1-0]    156.330354 s: UB960_RX2: RX_PORT_NUM = RX2 
[IPU1-0]    156.330445 s: UB960_RX2: PORT_PASS=1 
[IPU1-0]    156.330506 s: UB960_RX2: LOCK_STS=1 
[IPU1-0]    156.331360 s: UB960_RX2: FREQ_STABLE DETECTED 
[IPU1-0]    156.333343 s: UB960_RX2: Line count 1080 
[IPU1-0]    156.335356 s: UB960_RX2: Line Length 3840 
[IPU1-0]    156.336363 s: UB960_RX2: CSI_RX_STS 0x00 
[IPU1-0]    156.337522 s: UB960_RX2: CSI_ERR_COUNTER 0 
[IPU1-0]    156.338345 s:   UB953:Device STS = 0xC0 
[IPU1-0]    156.339352 s:   UB953:GENERAL_STATUS = 0x45 
[IPU1-0]    156.339443 s:    LINE_LEN_CHG 
[IPU1-0]    156.339504 s:    FREQ_STABLE DETECTED 
[IPU1-0]    156.339565 s:    LINE_CNT_CHG DETECTED 
[IPU1-0]    156.340419 s:   UB953:GPIO_PIN_STS = 0x04 
[IPU1-0]    156.341365 s:   UB953:BIST_ERR_CNT = 0x00 
[IPU1-0]    156.342524 s:   UB953:CRC_ERR_CNT1 = 0x00 
[IPU1-0]    156.343347 s:   UB953:CRC_ERR_CNT2 = 0x00 
[IPU1-0]    156.344354 s:   UB953:CSI_ERR_CNT = 0x00 
[IPU1-0]    156.345360 s:   UB953:CSI_ERR_STATUS = 0x00 
[IPU1-0]    156.346336 s:   UB953:CSI_ERR_DLANE01 = 0x00 
[IPU1-0]    156.347526 s:   UB953:CSI_ERR_DLANE23 = 0x00 
[IPU1-0]    156.348349 s:   UB953:CSI_ERR_CLK_LANE = 0x00 
[IPU1-0]    156.349356 s:   UB953:CSI_PKT_HDR_VC_ID = 0x1E 
[IPU1-0]    156.350362 s:   UB953:PKT_HDR_WC_LSB = 0x00 
[IPU1-0]    156.351338 s:   UB953:PKT_HDR_WC_MSB = 0x0F 
[IPU1-0]    156.352528 s:   UB953: CSI_ECC = 0x14 
[IPU1-0]    156.362502 s: RDACM51: STV0971 device ID = 0x000003CB 
[IPU1-0]    156.371347 s: RDACM51: STV0971 cut number = 0x00000010 
[IPU1-0]    156.381351 s: RDACM51: Engineering tracking number = 0x00000000 
[IPU1-0]    156.391447 s: RDACM51: STV0971 firmware revision = 0x00000208 
[IPU1-0]    156.401360 s: RDACM51: STV0971 firmware patch revision = 0x0000000F 
[IPU1-0]    156.411334 s: RDACM51: STV0971 firmware UI revision = 0x00000067 
[IPU1-0]    156.421338 s: RDACM51: FSM_MODE = 0x00000004 
[IPU1-0]    156.430366 s: RDACM51: CMD_HOLD_STATE = 0x00000000 
[IPU1-0]    156.439364 s: RDACM51: SAFETY_STATUS= 0x00000000 
[IPU1-0]    156.448362 s: RDACM51: SAFETY_DURATION_USEC = 0x00000000 
[IPU1-0]    156.457603 s: RDACM51: INTER_FRAME_USEC = 0x00009A97 
[IPU1-0]    156.467577 s: RDACM51: TEMPERATURE = 0x00000032 
[IPU1-0]    156.477520 s: RDACM51: FRAME_COUNTER = 0x000007C3 
[IPU1-0]    156.486335 s: RDACM51: FRAME_CORRUPTED = 0x00000000 
[IPU1-0]    156.496339 s: RDACM51: FRAME_LENGTH = 0x00000A6B 
[IPU1-0]    156.506344 s: RDACM51: LINE_LENGTH = 0x000009C4 
[IPU1-0]    156.516348 s: RDACM51: X_ADDR_START = 0x00000000 
[IPU1-0]    156.526352 s: RDACM51: Y_ADDR_START = 0x00000000 
[IPU1-0]    156.536356 s: RDACM51: X_OUTPUT_SIZE = 0x00000780 
[IPU1-0]    156.545354 s: RDACM51: Y_OUTPUT_SIZE = 0x00000438 
[IPU1-0]    156.554352 s: RDACM51: STATUS_LINE_DATA = 0x00000000 
[IPU1-0]    156.555358 s: Check status for RX chan 3: 
[IPU1-0]    156.558348 s: UB960_RX3: RX_PORT_NUM = RX3 
[IPU1-0]    156.558439 s: UB960_RX3: PORT_PASS=1 
[IPU1-0]    156.558531 s: UB960_RX3: LOCK_STS=1 
[IPU1-0]    156.559354 s: UB960_RX3: FREQ_STABLE DETECTED 
[IPU1-0]    156.561367 s: UB960_RX3: Line count 1080 
[IPU1-0]    156.563350 s: UB960_RX3: Line Length 3840 
[IPU1-0]    156.564387 s: UB960_RX3: CSI_RX_STS 0x00 
[IPU1-0]    156.565363 s: UB960_RX3: CSI_ERR_COUNTER 0 
[IPU1-0]    156.566369 s:   UB953:Device STS = 0xC0 
[IPU1-0]    156.567528 s:   UB953:GENERAL_STATUS = 0x45 
[IPU1-0]    156.567620 s:    LINE_LEN_CHG 
[IPU1-0]    156.567681 s:    FREQ_STABLE DETECTED 
[IPU1-0]    156.567711 s:    LINE_CNT_CHG DETECTED 
[IPU1-0]    156.568352 s:   UB953:GPIO_PIN_STS = 0x04 
[IPU1-0]    156.569419 s:   UB953:BIST_ERR_CNT = 0x00 
[IPU1-0]    156.570365 s:   UB953:CRC_ERR_CNT1 = 0x00 
[IPU1-0]    156.571341 s:   UB953:CRC_ERR_CNT2 = 0x00 
[IPU1-0]    156.572530 s:   UB953:CSI_ERR_CNT = 0x00 
[IPU1-0]    156.573354 s:   UB953:CSI_ERR_STATUS = 0x00 
[IPU1-0]    156.574361 s:   UB953:CSI_ERR_DLANE01 = 0x00 
[IPU1-0]    156.575367 s:   UB953:CSI_ERR_DLANE23 = 0x00 
[IPU1-0]    156.576374 s:   UB953:CSI_ERR_CLK_LANE = 0x00 
[IPU1-0]    156.577533 s:   UB953:CSI_PKT_HDR_VC_ID = 0x1E 
[IPU1-0]    156.578356 s:   UB953:PKT_HDR_WC_LSB = 0x00 
[IPU1-0]    156.579363 s:   UB953:PKT_HDR_WC_MSB = 0x0F 
[IPU1-0]    156.580369 s:   UB953: CSI_ECC = 0x14 
[IPU1-0]    156.589336 s: RDACM51: STV0971 device ID = 0x000003CB 
[IPU1-0]    156.598365 s: RDACM51: STV0971 cut number = 0x00000010 
[IPU1-0]    156.607515 s: RDACM51: Engineering tracking number = 0x00000000 
[IPU1-0]    156.617550 s: RDACM51: STV0971 firmware revision = 0x00000208 
[IPU1-0]    156.626364 s: RDACM51: STV0971 firmware patch revision = 0x0000000F 
[IPU1-0]    156.635362 s: RDACM51: STV0971 firmware UI revision = 0x00000067 
[IPU1-0]    156.644360 s: RDACM51: FSM_MODE = 0x00000004 
[IPU1-0]    156.653358 s: RDACM51: CMD_HOLD_STATE = 0x00000000 
[IPU1-0]    156.662538 s: RDACM51: SAFETY_STATUS= 0x00000000 
[IPU1-0]    156.672543 s: RDACM51: SAFETY_DURATION_USEC = 0x00000000 
[IPU1-0]    156.682547 s: RDACM51: INTER_FRAME_USEC = 0x0000327D 
[IPU1-0]    156.691362 s: RDACM51: TEMPERATURE = 0x0000003C 
[IPU1-0]    156.701366 s: RDACM51: FRAME_COUNTER = 0x00000CF2 
[IPU1-0]    156.710364 s: RDACM51: FRAME_CORRUPTED = 0x00000000 
[IPU1-0]    156.719392 s: RDACM51: FRAME_LENGTH = 0x00000641 
[IPU1-0]    156.728359 s: RDACM51: LINE_LENGTH = 0x000009C4 
[IPU1-0]    156.737540 s: RDACM51: X_ADDR_START = 0x00000000 
[IPU1-0]    156.746355 s: RDACM51: Y_ADDR_START = 0x00000000 
[IPU1-0]    156.756359 s: RDACM51: X_OUTPUT_SIZE = 0x00000780 
[IPU1-0]    156.765357 s: RDACM51: Y_OUTPUT_SIZE = 0x00000438 
[IPU1-0]    156.774385 s: RDACM51: STATUS_LINE_DATA = 0x00000000 
[IPU1-0]    156.774476 s: FPDLink_camera_print_status End ...
[IPU1-0]    156.774537 s: FPDLink_camera_print_status Start ...
[IPU1-0]    156.774629 s: ##################################################
[IPU1-0]    156.774690 s: ########## Check status for CSI port 1 ##########
[IPU1-0]    156.774781 s: ##################################################
[IPU1-0]    156.775361 s: UB960: Forwarding is not synchronized for CSI-2 output port 1 
[IPU1-0]    156.775483 s: UB960: Forwarding is not synchronized for CSI-2 output port 0 
[IPU1-0]    156.778381 s: UB960: CSI0_FRAME_COUNT = 7291 
[IPU1-0]    156.780363 s: UB960: CSI0_FRAME_ERR_COUNT = 0 
[IPU1-0]    156.782559 s: UB960: CSI0_LINE_COUNT =  65535 
[IPU1-0]    156.784359 s: UB960: CSI0_LINE_ERR_COUNT = 0 
[IPU1-0]    156.785365 s: Check status for RX chan 0: 
[IPU1-0]    156.788385 s: UB960_RX0: RX_PORT_NUM = RX0 
[IPU1-0]    156.788446 s: UB960_RX0: PORT_PASS=1 
[IPU1-0]    156.788537 s: UB960_RX0: LOCK_STS=1 
[IPU1-0]    156.789361 s: UB960_RX0: FREQ_STABLE DETECTED 
[IPU1-0]    156.791374 s: UB960_RX0: Line count 1114 
[IPU1-0]    156.793356 s: UB960_RX0: Line Length 2904 
[IPU1-0]    156.794363 s: UB960_RX0: CSI_RX_STS 0x00 
[IPU1-0]    156.795369 s: UB960_RX0: CSI_ERR_COUNTER 0 
[IPU1-0]    156.796376 s:   UB953:Device STS = 0xC0 
[IPU1-0]    156.797535 s:   UB953:GENERAL_STATUS = 0x45 
[IPU1-0]    156.797627 s:    LINE_LEN_CHG 
[IPU1-0]    156.797688 s:    FREQ_STABLE DETECTED 
[IPU1-0]    156.797749 s:    LINE_CNT_CHG DETECTED 
[IPU1-0]    156.798359 s:   UB953:GPIO_PIN_STS = 0x00 
[IPU1-0]    156.799365 s:   UB953:BIST_ERR_CNT = 0x00 
[IPU1-0]    156.800372 s:   UB953:CRC_ERR_CNT1 = 0x00 
[IPU1-0]    156.801378 s:   UB953:CRC_ERR_CNT2 = 0x00 
[IPU1-0]    156.802537 s:   UB953:CSI_ERR_CNT = 0x00 
[IPU1-0]    156.803361 s:   UB953:CSI_ERR_STATUS = 0x00 
[IPU1-0]    156.804367 s:   UB953:CSI_ERR_DLANE01 = 0x00 
[IPU1-0]    156.805374 s:   UB953:CSI_ERR_DLANE23 = 0x00 
[IPU1-0]    156.806350 s:   UB953:CSI_ERR_CLK_LANE = 0x00 
[IPU1-0]    156.807539 s:   UB953:CSI_PKT_HDR_VC_ID = 0x12 
[IPU1-0]    156.808363 s:   UB953:PKT_HDR_WC_LSB = 0x58 
[IPU1-0]    156.809369 s:   UB953:PKT_HDR_WC_MSB = 0x0B 
[IPU1-0]    156.810376 s:   UB953: CSI_ECC = 0x0A 
[IPU1-0]    156.811352 s: Check status for RX chan 1: 
[IPU1-0]    156.814371 s: UB960_RX1: RX_PORT_NUM = RX1 
[IPU1-0]    156.814463 s: UB960_RX1: PORT_PASS=1 
[IPU1-0]    156.814524 s: UB960_RX1: LOCK_STS=1 
[IPU1-0]    156.815378 s: UB960_RX1: FREQ_STABLE DETECTED 
[IPU1-0]    156.817544 s: UB960_RX1: Line count 720 
[IPU1-0]    156.819374 s: UB960_RX1: Line Length 2560 
[IPU1-0]    156.820380 s: UB960_RX1: CSI_RX_STS 0x00 
[IPU1-0]    156.821356 s: UB960_RX1: CSI_ERR_COUNTER 0 
[IPU1-0]    156.822607 s:   UB913:#General Status 0x0C = 0x15 
[IPU1-0]    156.823369 s:   UB913:#General Status 0x1C = 0x00 
[IPU1-0]    156.824376 s: Check status for RX chan 2: 
[IPU1-0]    156.827548 s: UB960_RX2: RX_PORT_NUM = RX2 
[IPU1-0]    156.828371 s: UB960_RX2: NO_FPD3_CLK DETECTED 
[IPU1-0]    156.830384 s: UB960_RX2: Line count 0 
[IPU1-0]    156.832550 s: UB960_RX2: Line Length 0 
[IPU1-0]    156.833374 s: UB960_RX2: CSI_RX_STS 0x00 
[IPU1-0]    156.834350 s: UB960_RX2: CSI_ERR_COUNTER 0 
[IPU1-0]    156.835356 s: Check status for RX chan 3: 
[IPU1-0]    156.838406 s: UB960_RX3: RX_PORT_NUM = RX3 
[IPU1-0]    156.839382 s: UB960_RX3: NO_FPD3_CLK DETECTED 
[IPU1-0]    156.841365 s: UB960_RX3: Line count 0 
[IPU1-0]    156.843439 s: UB960_RX3: Line Length 0 
[IPU1-0]    156.844354 s: UB960_RX3: CSI_RX_STS 0x00 
[IPU1-0]    156.845360 s: UB960_RX3: CSI_ERR_COUNTER 0 
[IPU1-0]    156.845452 s: FPDLink_camera_print_status End ...
[IPU1-0]    156.845513 s:

cal2vip_config.txt

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../ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/vps/src/vpslib/hal/src/vpshal_isscal.c
/**************************************************************************************/
static int32_t CalSetVportCfg(const isshalCalInstObj_t *pInst,
                              const vpsissCalVPort_t   *cfg,
                              uint32_t                  cportId)
{
    uint32_t          baseAddr;
    volatile uint32_t reg;
    GT_assert(VpsHalTrace, (NULL != pInst));
    GT_assert(VpsHalTrace, (NULL != cfg));
    baseAddr = pInst->baseAddr;
    GT_assert(VpsHalTrace, (0U != baseAddr));
    reg  = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL1);
    reg &= ~CAL_VPORT_CTRL1_PCLK_MASK;
    if((uint32_t)TRUE == cfg->enable)
    {
        reg &= ~(CAL_VPORT_CTRL1_XBLK_MASK | CAL_VPORT_CTRL1_YBLK_MASK |
                 CAL_VPORT_CTRL1_WIDTH_MASK);
        reg |= CAL_VPORT_CTRL1_PCLK_MASK & cfg->pixClock;
        reg |= CAL_VPORT_CTRL1_XBLK_MASK &
               (cfg->xBlk << CAL_VPORT_CTRL1_XBLK_SHIFT);
        reg |= CAL_VPORT_CTRL1_YBLK_MASK &
               (cfg->yBlk << CAL_VPORT_CTRL1_YBLK_SHIFT);
        if(0x0U != cfg->width)
        {
            reg |= CAL_VPORT_CTRL1_WIDTH_MASK;
        }
        HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg);
        reg  = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL2);
        reg &=
            ~(CAL_VPORT_CTRL2_RDY_THR_MASK | CAL_VPORT_CTRL2_FSM_RESET_MASK |
              CAL_VPORT_CTRL2_FS_RESETS_MASK |
              CAL_VPORT_CTRL2_FREERUNNING_MASK |
              CAL_VPORT_CTRL2_CPORT_MASK);
        reg |= CAL_VPORT_CTRL2_CPORT_MASK & cportId;
        if((uint32_t)TRUE == cfg->freeRun)
        {
            reg |= CAL_VPORT_CTRL2_FREERUNNING_MASK;
        }
        if((uint32_t)TRUE == cfg->fsReset)
        {
            reg |= CAL_VPORT_CTRL2_FS_RESETS_MASK;
        }
        reg |= CAL_VPORT_CTRL2_RDY_THR_MASK &
               (cfg->rdyThr << CAL_VPORT_CTRL2_RDY_THR_SHIFT);
        /* Enable transmission on vports 2, 3 & 4 */
        reg = reg | 0x20U;
        /* Configure the cport ID's */
        reg = reg | 0x01U;
        HW_WR_REG32(baseAddr + CAL_VPORT_CTRL2, reg);
    }
    else
    {
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

../ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/vps/src/vpslib/hal/src/vpshal_isscal.c

/**************************************************************************************/
static int32_t CalSetVportCfg(const isshalCalInstObj_t *pInst,
                              const vpsissCalVPort_t   *cfg,
                              uint32_t                  cportId)
{
    uint32_t          baseAddr;
    volatile uint32_t reg;

    GT_assert(VpsHalTrace, (NULL != pInst));
    GT_assert(VpsHalTrace, (NULL != cfg));

    baseAddr = pInst->baseAddr;
    GT_assert(VpsHalTrace, (0U != baseAddr));

    reg  = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL1);
    reg &= ~CAL_VPORT_CTRL1_PCLK_MASK;
    if((uint32_t)TRUE == cfg->enable)
    {
        reg &= ~(CAL_VPORT_CTRL1_XBLK_MASK | CAL_VPORT_CTRL1_YBLK_MASK |
                 CAL_VPORT_CTRL1_WIDTH_MASK);

        reg |= CAL_VPORT_CTRL1_PCLK_MASK & cfg->pixClock;

        reg |= CAL_VPORT_CTRL1_XBLK_MASK &
               (cfg->xBlk << CAL_VPORT_CTRL1_XBLK_SHIFT);

        reg |= CAL_VPORT_CTRL1_YBLK_MASK &
               (cfg->yBlk << CAL_VPORT_CTRL1_YBLK_SHIFT);

        if(0x0U != cfg->width)
        {
            reg |= CAL_VPORT_CTRL1_WIDTH_MASK;
        }
        HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg);

        reg  = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL2);
        reg &=
            ~(CAL_VPORT_CTRL2_RDY_THR_MASK | CAL_VPORT_CTRL2_FSM_RESET_MASK |
              CAL_VPORT_CTRL2_FS_RESETS_MASK |
              CAL_VPORT_CTRL2_FREERUNNING_MASK |
              CAL_VPORT_CTRL2_CPORT_MASK);

        reg |= CAL_VPORT_CTRL2_CPORT_MASK & cportId;

        if((uint32_t)TRUE == cfg->freeRun)
        {
            reg |= CAL_VPORT_CTRL2_FREERUNNING_MASK;
        }

        if((uint32_t)TRUE == cfg->fsReset)
        {
            reg |= CAL_VPORT_CTRL2_FS_RESETS_MASK;
        }

        reg |= CAL_VPORT_CTRL2_RDY_THR_MASK &
               (cfg->rdyThr << CAL_VPORT_CTRL2_RDY_THR_SHIFT);

        /* Enable transmission on vports 2, 3 & 4 */
        reg = reg | 0x20U;
        /* Configure the cport ID's */
        reg = reg | 0x01U;
        HW_WR_REG32(baseAddr + CAL_VPORT_CTRL2, reg);
    }
    else
    {
        HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg);
    }

    return FVID2_SOK;
}


!!!!!!!     see  Write2VIP
../vision_sdk/links_fw/src/rtos/links_ipu/iss_capture/issCaptureLink_drv.c

/**************************************************************************************/
Void IssCaptureLink_drvSetDrvCfg(IssCaptureLink_Obj *pObj)
{
    Vps_CaptCreateParams        *drvCreatePrms;
    vpsissCalCmplxIoCfg_t       *drvCmplxIoCfg;
    IssCaptureLink_Csi2Params   *csi2Params;
    vpsissCalCfg_t              *drvCalCfg;
    IssCaptureLink_OutParams    *outPrms;
    UInt32 strmId, cmplxIoId, numPixProcUsed;

    drvCreatePrms = &pObj->drvCreatePrms;

    Fvid2CbParams_init(&pObj->drvCbPrms);
    VpsCaptCreateParams_init(drvCreatePrms);
    vpsissCalCfg_t_init(&pObj->drvCalCfg);

    pObj->drvInstId    = VPS_CAPT_INST_ISS_CAL_A;

    pObj->drvCbPrms.cbFxn   = &issCaptDrvCallback;
    pObj->drvCbPrms.appData = pObj;

    drvCreatePrms->videoIfMode     = pObj->createArgs.videoIfMode;
    drvCreatePrms->videoIfWidth    = pObj->createArgs.videoIfWidth;
    drvCreatePrms->bufCaptMode     = pObj->createArgs.bufCaptMode;
    drvCreatePrms->numCh           = 1U;
    /* CAL Treats channels as streams with in CAL */
    drvCreatePrms->numStream       = pObj->createArgs.numCh;
    drvCreatePrms->pAdditionalArgs = &pObj->drvIssCaptureCreatePrms;


    for (strmId = 0U; strmId < pObj->createArgs.numCh; strmId++)
    {
        drvCreatePrms->chNumMap[strmId][0U] =
                Vps_captMakeChNum(pObj->drvInstId, strmId, 0U);
    }

    memset(&pObj->drvIssCaptureCreatePrms, (Int32) 0,
            sizeof(pObj->drvIssCaptureCreatePrms));

    pObj->drvCalCfg.numStream = pObj->createArgs.numCh;

    numPixProcUsed = 0U;

    for (strmId = 0U; strmId < pObj->createArgs.numCh; strmId++)
    {
        drvCalCfg = &pObj->drvCalCfg;
        outPrms   = &pObj->createArgs.outParams[strmId];

        drvCalCfg->streamId[strmId] = strmId;
        drvCalCfg->inFmt[strmId].width  = outPrms->width;
        drvCalCfg->inFmt[strmId].height = outPrms->height;
        drvCalCfg->inFmt[strmId].pitch[0U] =
                                pObj->info.queInfo[0].chInfo[strmId].pitch[0];
        drvCalCfg->inFmt[strmId].bpp = outPrms->outBpp;
        drvCalCfg->inFmt[strmId].dataFormat = 0U;
        drvCalCfg->writeToMem[strmId] = (UInt32)TRUE;
        drvCalCfg->streamType[strmId] = VPS_ISS_CAL_TAG_PIX_DATA;
        drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)FALSE;
        drvCalCfg->isBysOutCfgValid[strmId]  = (UInt32)FALSE;
        drvCalCfg->bysInEnable[strmId]       = (UInt32)FALSE;
        drvCalCfg->isVportCfgValid[strmId]   = (UInt32)FALSE;

        if(SYSTEM_VIFM_SCH_CPI == pObj->createArgs.videoIfMode)
        {
            UTILS_assert(0U == strmId);
            drvCreatePrms->numCh = 1U;

            pObj->drvIssCaptureCreatePrms.subModules[strmId] =
                VPS_ISS_CAPT_CAL_SUB_CPORT_ID |
                VPS_ISS_CAPT_CAL_SUB_DMA_WR_ID |
                VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID |
                VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID |
                VPS_ISS_CAPT_CAL_SUB_BYS_IN_ID;

            drvCalCfg->bysInEnable[strmId] = (UInt32)TRUE;

            if(pObj->createArgs.videoIfWidth == SYSTEM_VIFW_10BIT)
            {
                drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW10;
            }
            else if(pObj->createArgs.videoIfWidth == SYSTEM_VIFW_12BIT)
            {
                drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW12;
            }
            else if(pObj->createArgs.videoIfWidth == SYSTEM_VIFW_14BIT)
            {
                drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW14;
            }
            else
            {
                drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW12;
            }
        }
        else if(SYSTEM_VIFM_SCH_CSI2 == pObj->createArgs.videoIfMode)
        {
            pObj->drvIssCaptureCreatePrms.subModules[strmId] =
                                VPS_ISS_CAPT_CAL_SUB_CSI2_ID |
                                VPS_ISS_CAPT_CAL_SUB_CPORT_ID |
                                VPS_ISS_CAPT_CAL_SUB_DMA_WR_ID |
                                VPS_ISS_CAPT_CAL_SUB_PIX_EXTRACT_ID |
                                VPS_ISS_CAPT_CAL_SUB_DPCM_DEC_ID |
                                VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID |
                                VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID;

            if (0U == outPrms->phyInstance)
            {
                pObj->drvIssCaptureCreatePrms.subModules[strmId] |=
                                VPS_ISS_CAPT_CAL_SUB_PPI_ID_0;
                drvCalCfg->cmplxIoId[strmId] = 0U;
            }
            else if (1U == outPrms->phyInstance)
            {
                pObj->drvIssCaptureCreatePrms.subModules[strmId] |=
                                VPS_ISS_CAPT_CAL_SUB_PPI_ID_1;
                drvCalCfg->cmplxIoId[strmId] = 1U;
            }
            else
            {
                /* Illelagl PHY instance ID */
                UTILS_assert((Bool) 0U);
            }

            drvCalCfg->csi2DataFormat[strmId] =
                            (vpsissCalCsi2DataFormat) outPrms->inCsi2DataFormat;
        }
        else
        {
            /* Illegal interface */
            UTILS_assert((Bool) 0U);
        }

        drvCalCfg->csi2VirtualChanNo[strmId] = outPrms->inCsi2VirtualChanNum;

        if (SYSTEM_BPP_BITS12_PACKED_MIPI == drvCalCfg->inFmt[strmId].bpp)
        {
            drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)FALSE;

            /* These modules are not required */
            pObj->drvIssCaptureCreatePrms.subModules[strmId] &=
                                    (UInt32)
                                    (~ (VPS_ISS_CAPT_CAL_SUB_PIX_EXTRACT_ID |
                                        VPS_ISS_CAPT_CAL_SUB_DPCM_DEC_ID |
                                        VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID |
                                        VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID));

            drvCalCfg->inFmt[strmId].width =
                (drvCalCfg->inFmt[strmId].width * 3u) / 2u;
        }
        else
        {
            drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)TRUE;
        }
        drvCalCfg->pixProcCfg[strmId].decCodec = VPS_ISS_CAL_DPCM_DEC_BYPASS;
        drvCalCfg->pixProcCfg[strmId].enableDpcmInitContext = (UInt32)FALSE;
        drvCalCfg->pixProcCfg[strmId].encCodec = VPS_ISS_CAL_DPCM_ENC_BYPASS;
        drvCalCfg->pixProcCfg[strmId].pack     = VPS_ISS_CAL_PIX_PACK_B16;

        if (((UInt32) TRUE == drvCalCfg->isPixProcCfgValid[strmId]) &&
            (VPS_ISS_CAL_MAX_PIX_PROC_CONTEXT <= numPixProcUsed))
        {
            drvCalCfg->isPixProcCfgValid[strmId] = FALSE;
            pObj->drvIssCaptureCreatePrms.subModules[strmId] &=
                                    (UInt32)
                                    (~ (VPS_ISS_CAPT_CAL_SUB_PIX_EXTRACT_ID |
                                        VPS_ISS_CAPT_CAL_SUB_DPCM_DEC_ID |
                                        VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID |
                                        VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID));

            Vps_printf(" ISSCAPTURE: Warning: Available pixel processing "
                        "contexts is %d, "
                    "Turning OFF pixel processing contexts for streams %d \n",
                    VPS_ISS_CAL_MAX_PIX_PROC_CONTEXT, strmId);
        }

        if (outPrms->Write2VIP)
        {
            drvCalCfg->writeToMem[strmId] = FALSE;

//            pObj->drvIssCaptureCreatePrms.subModules[strmId] &=(UInt32)(~VPS_ISS_CAPT_CAL_SUB_DMA_WR_ID);
//            pObj->drvIssCaptureCreatePrms.subModules[strmId] |= VPS_ISS_CAPT_CAL_SUB_VPORT_ID;

//            pObj->drvIssCaptureCreatePrms.subModules[strmId] =  VPS_ISS_CAPT_CAL_SUB_CSI2_ID |
//                                                                VPS_ISS_CAPT_CAL_SUB_CPORT_ID |
//                                                                VPS_ISS_CAPT_CAL_SUB_VPORT_ID;

//            drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)FALSE;
            drvCalCfg->writeToMem[strmId] = (UInt32)FALSE;

            drvCalCfg->isVportCfgValid[strmId]    = (UInt32)TRUE;
            drvCalCfg->vportCfg[strmId].enable   = (UInt32)TRUE;
            drvCalCfg->vportCfg[strmId].pixClock = 20480U;
            drvCalCfg->vportCfg[strmId].width   = 0U;
            drvCalCfg->vportCfg[strmId].xBlk    = 0x4U;
            drvCalCfg->vportCfg[strmId].yBlk    = 0x3CU;
            drvCalCfg->vportCfg[strmId].rdyThr  = 0U;
            drvCalCfg->vportCfg[strmId].fsReset = TRUE;
//            drvCalCfg->vportCfg[strmId].freeRun = TRUE;

//            drvCalCfg->isPixProcCfgValid[strmId]   = TRUE;
//            drvCalCfg->pixProcCfg[strmId].decCodec = VPS_ISS_CAL_DPCM_DEC_BYPASS;
//            drvCalCfg->pixProcCfg[strmId].enableDpcmInitContext = FALSE;
//            drvCalCfg->pixProcCfg[strmId].encCodec = VPS_ISS_CAL_DPCM_ENC_BYPASS;
//            drvCalCfg->pixProcCfg[strmId].pack     = VPS_ISS_CAL_PIX_PACK_B16;

        }

        switch((System_Csi2DataFormat)(drvCalCfg->csi2DataFormat[strmId]))
        {
            case SYSTEM_CSI2_RAW10:
                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B10_MIPI;
                if (((SYSTEM_DF_YUV422I_UYVY == outPrms->outDataFormat) ||
                     ((SYSTEM_DF_YUV422I_YUYV == outPrms->outDataFormat))) ||
                    ((SYSTEM_DF_YUV422I_YVYU == outPrms->outDataFormat) ||
                     ((SYSTEM_DF_YUV422I_VYUY == outPrms->outDataFormat))))
                {
                    drvCalCfg->pixProcCfg[strmId].extract =
                                                    VPS_ISS_CAL_PIX_EXRCT_B8;
                    drvCalCfg->pixProcCfg[strmId].pack =
                                                    VPS_ISS_CAL_PIX_PACK_B8;
                }
                break;
            case SYSTEM_CSI2_RAW12:
                //drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B12_MIPI;
//                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B16_LE;
                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B12_MIPI;
                drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B12_MIPI;
                break;
            case SYSTEM_CSI2_RAW14:
                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B14_MIPI;
                break;
           case SYSTEM_CSI2_RAW8:
                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8;
                drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8;
                break;
           case SYSTEM_CSI2_YUV420_8B:
           case SYSTEM_CSI2_YUV420_8B_LEGACY:
           case SYSTEM_CSI2_YUV420_8B_CHROMA_SHIFT:
           case SYSTEM_CSI2_YUV422_8B:
                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B16_LE;
                drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B16;
//                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8;
//                drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8;
                break;
//           case SYSTEM_CSI2_YUV420_8B:
//           case SYSTEM_CSI2_YUV420_8B_LEGACY:
//           case SYSTEM_CSI2_YUV420_8B_CHROMA_SHIFT:
//           case SYSTEM_CSI2_YUV422_8B:
//                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8;
//                drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8;
//                break;
            case SYSTEM_CSI2_RGB888:
                drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8;
                drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8;
                break;
            default:
                UTILS_assert((Bool) 0U);
                break;
        }
        if ((Bool)TRUE == drvCalCfg->isPixProcCfgValid[strmId])
        {
            numPixProcUsed++;
        }
    }

    for (cmplxIoId = 0U; cmplxIoId < VPS_ISS_CAL_MAX_CMPLXIO_INST; cmplxIoId ++)
    {
        csi2Params = &pObj->createArgs.csi2Params[cmplxIoId];
        drvCmplxIoCfg = &pObj->drvIssCaptureCreatePrms.cmplxIoCfg[cmplxIoId];

        pObj->drvIssCaptureCreatePrms.isCmplxIoCfgValid[cmplxIoId] =
                                                csi2Params->isCmplxIoCfgValid;

        pObj->drvIssCaptureCreatePrms.csi2PhyClock[cmplxIoId] =
                                                csi2Params->csi2PhyClk;

        if ((UInt32)TRUE == csi2Params->isCmplxIoCfgValid)
        {
            drvCmplxIoCfg->enable             = (UInt32)TRUE;
            drvCmplxIoCfg->pwrAuto            = (UInt32)TRUE;
            drvCmplxIoCfg->clockLane.pol      =
                                    csi2Params->cmplxIoCfg.clockLane.pol;
            drvCmplxIoCfg->clockLane.position =
                                    csi2Params->cmplxIoCfg.clockLane.position;
            drvCmplxIoCfg->data1Lane.pol      =
                                    csi2Params->cmplxIoCfg.data1Lane.pol;
            drvCmplxIoCfg->data1Lane.position =
                                    csi2Params->cmplxIoCfg.data1Lane.position;
            drvCmplxIoCfg->data2Lane.pol      =
                                    csi2Params->cmplxIoCfg.data2Lane.pol;
            drvCmplxIoCfg->data2Lane.position =
                                    csi2Params->cmplxIoCfg.data2Lane.position;
            drvCmplxIoCfg->data3Lane.pol      =
                                    csi2Params->cmplxIoCfg.data3Lane.pol;
            drvCmplxIoCfg->data3Lane.position =
                                    csi2Params->cmplxIoCfg.data3Lane.position;
            drvCmplxIoCfg->data4Lane.pol      =
                                    csi2Params->cmplxIoCfg.data4Lane.pol;
            drvCmplxIoCfg->data4Lane.position =
                                    csi2Params->cmplxIoCfg.data4Lane.position;
        }
        else
        {
            drvCmplxIoCfg->enable             = (UInt32)FALSE;
            drvCmplxIoCfg->pwrAuto            = (UInt32)FALSE;
        }
    }
}


../ti_components/drivers/pdk_01_10_03_07/packages/ti/csl/soc/tda2px/hw_ctrl_core_pad.h
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_SHIFT                                                    (12U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_MASK                                                     (0x00001000U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_PADS                                                     (0U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_CAL                                                      (1U)

#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_SHIFT                                                    (11U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_MASK                                                     (0x00000800U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_PADS                                                     (0U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_CAL                                                      (1U)

#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_SHIFT                                                    (10U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_MASK                                                     (0x00000400U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_PADS                                                     (0U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_CAL                                                      (1U)

#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_SHIFT                                                    (9U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_MASK                                                     (0x00000200U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_PADS                                                     (0U)
#define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_CAL                                                      (1U)


../ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/stw_lld/platform/src/tda2xx/platform_tda2xx.c
/**************************************************************************************/
void PlatformCAL2VPortConfig(uint32_t port, uint32_t enable_mask) /* port - 1..4 for vport1A..4A, enable_mask - 1=enable 0=disable */
{
    switch (port) {
    case 1:
        HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW,
            CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A,
            enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_PADS);
        break;
    case 2:
        HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW,
            CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A,
            enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_PADS);
        break;
    case 3:
        HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW,
            CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A,
            enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_PADS);
        break;
    case 4:
        HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW,
            CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A,
            enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_PADS);
        break;
    default:
        break;
    }
}



config.c

/**************************************************************************************/
Void ArrivalInitBaseIssCapturePrms(struct ArrivalApp *appObj)
{
    UInt32 chan_idx=0;
    UInt32 port_idx=0;
    UInt32 csi_chan_idx=0;
//    UInt32 max_width=0;
//    UInt32 max_height=0;
    IssCaptureLink_CreateParams *IssCapturePrm = &appObj->graphObj.IssCaptureLinkPrm;

    IssCaptureLink_CreateParams_Init(IssCapturePrm);

    IssCapturePrm->videoIfMode = SYSTEM_VIFM_SCH_CSI2;
    IssCapturePrm->videoIfWidth = SYSTEM_VIFW_4LANES;
    IssCapturePrm->bufCaptMode =  SYSTEM_CAPT_BCM_LAST_FRM_REPEAT;

    for (port_idx=0;port_idx<ISSCAPT_LINK_MAX_CMPLXIO_INST;port_idx++)
    { /* config CSI phy port */
        IssCapturePrm->csi2Params[port_idx].isCmplxIoCfgValid = TRUE;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.clockLane.pol = FALSE;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.clockLane.position = 1;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data1Lane.pol = FALSE;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data1Lane.position = 2;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data2Lane.pol = FALSE;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data2Lane.position = 3;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data3Lane.pol = FALSE;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data3Lane.position = 4;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data4Lane.pol = FALSE;
        IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data4Lane.position = 5;
        IssCapturePrm->csi2Params[port_idx].csi2PhyClk = CAPTURE_UB960_CSI2_CLOCK;
        if (port_idx == 1)
        {
            IssCapturePrm->csi2Params[1].cmplxIoCfg.data3Lane.position = 0;
            IssCapturePrm->csi2Params[1].cmplxIoCfg.data4Lane.position = 0;
        }
    }

    for (port_idx = 0; port_idx < ISSCAPT_LINK_MAX_CMPLXIO_INST; port_idx++)
    {
        for (chan_idx = 0; chan_idx < appObj->camPort[port_idx].remote_chan_count; chan_idx++)
        {
            struct remote_chan *remote_chan = &appObj->camPort[port_idx].remote_chan[chan_idx];
            IssCaptureLink_OutParams *outParams = &IssCapturePrm->outParams[csi_chan_idx];
            if (remote_chan->enable == TRUE)
            {
                outParams->width = remote_chan->inWidth;
                outParams->height = remote_chan->inHeight;
                outParams->maxWidth = remote_chan->inWidth;
                outParams->maxHeight = remote_chan->inHeight;
                outParams->dataFormat = remote_chan->inFormat;
                outParams->inCsi2DataFormat = remote_chan->csiFormat;
                outParams->inCsi2VirtualChanNum = (4*port_idx) + csi_chan_idx;
                outParams->numOutBuf = PIPELINE_NUM_BUF_PER_CH;
                outParams->outDataFormat = remote_chan->inFormat;
                outParams->phyInstance = appObj->camPort[port_idx].CSI_id;
                outParams->outBpp = GetSytemBppByCsiFormat(outParams->inCsi2DataFormat);
                outParams->Write2VIP = FALSE;
                csi_chan_idx++;
                if (csi_chan_idx == ISSCAPT_LINK_MAX_CH)
                    break;
            }
        }
    }

    IssCapturePrm->outParams[0].Write2VIP = TRUE;
    IssCapturePrm->outParams[1].Write2VIP = TRUE;
    IssCapturePrm->outParams[2].Write2VIP = TRUE;
    IssCapturePrm->outParams[3].Write2VIP = TRUE;
    IssCapturePrm->outParams[4].Write2VIP = FALSE;
    IssCapturePrm->outParams[5].Write2VIP = FALSE;

    IssCapturePrm->numCh = csi_chan_idx;
    Vps_printf("ISS Capture config for %d channels \n", IssCapturePrm->numCh);


//    IssCapturePrm->callback = IssCaptureLink_CB;
//    IssCapturePrm->appObj = appObj;
    IssCapturePrm->allocBufferForRawDump = TRUE; //TODO
}


/**************************************************************************************/
Void InitBaseVipCapturePrms(struct mainApp *appObj)
{
    UInt32 chan_idx=0;
    CaptureLink_CreateParams *pVipCapturePrm = &appObj->graphObj.VipCaptureLinkPrm;
    IssCaptureLink_CreateParams *IssCaptureLinkPrm = &appObj->graphObj.IssCaptureLinkPrm;
    IssCaptureLink_OutParams *IssChPrms = NULL;
    CaptureLink_VipInstParams *pInstPrm;
    CaptureLink_InParams *pInprms;
    CaptureLink_OutParams *pOutprms;
    CaptureLink_VipScParams *pScPrm;
    CaptureLink_VipPortConfig    *pPortCfg;

    UInt32 portId[10];
    portId[0] = SYSTEM_CAPTURE_INST_VIP1_SLICE1_PORTA;
    portId[1] = SYSTEM_CAPTURE_INST_VIP1_SLICE2_PORTA;
    portId[2] = SYSTEM_CAPTURE_INST_VIP2_SLICE1_PORTA;
    portId[3] = SYSTEM_CAPTURE_INST_VIP2_SLICE2_PORTA;

    CaptureLink_CreateParams_Init(pVipCapturePrm);


    pVipCapturePrm->numVipInst = 4;
    pVipCapturePrm->numDssWbInst = 0;

    UTILS_assert(pVipCapturePrm->numVipInst<=SYSTEM_CAPTURE_VIP_INST_MAX);
    UTILS_assert(pVipCapturePrm->numDssWbInst<=SYSTEM_CAPTURE_DSSWB_INST_MAX);

    for (chan_idx=0; chan_idx<pVipCapturePrm->numVipInst; chan_idx++)
    {
        pInstPrm = &pVipCapturePrm->vipInst[chan_idx];
        IssChPrms = &IssCaptureLinkPrm->outParams[chan_idx];
        (void)IssChPrms;

        pInstPrm->vipInstId     =   portId[chan_idx];
        pInstPrm->videoIfMode   =   SYSTEM_VIFM_SCH_DS_HSYNC_VSYNC;
        pInstPrm->videoIfWidth  =   SYSTEM_VIFW_8BIT;
        pInstPrm->bufCaptMode   =   SYSTEM_CAPT_BCM_LAST_FRM_REPEAT;//SYSTEM_CAPT_BCM_FRM_DROP;//SYSTEM_CAPT_BCM_LAST_FRM_REPEAT;
        pInstPrm->numStream     =   1;

        pInprms = &pInstPrm->inParams;
        pInprms->width      =   1920;//IssChPrms->width;
        pInprms->height     =   1080;//IssChPrms->height;
        pInprms->dataFormat =   SYSTEM_DF_YUV422P; ////FIXME TODO
        pInprms->scanFormat =   SYSTEM_SF_PROGRESSIVE;

        pOutprms = &pInstPrm->outParams[0];
        pOutprms->width         =   pInprms->width;
        pOutprms->height        =   pInprms->height;
        pOutprms->dataFormat    =   SYSTEM_DF_YUV420SP_UV;
        pOutprms->maxWidth      =   pOutprms->width;
        pOutprms->maxHeight     =   pOutprms->height;
        pOutprms->scEnable      =   FALSE;

        /* sub-frame not supported, set to FALSE */
        pOutprms->subFrmPrms.subFrameEnable = FALSE;
        pOutprms->subFrmPrms.numLinesPerSubFrame = 0;
        pOutprms->frameSkipMask = 0;

        pScPrm = &pInstPrm->scPrms;
        pScPrm->inCropCfg.cropStartX = 0;
        pScPrm->inCropCfg.cropStartY = 0;
        pScPrm->inCropCfg.cropWidth = pInprms->width;
        pScPrm->inCropCfg.cropHeight = pInprms->height;

        pScPrm->scCfg.bypass       = FALSE;
        pScPrm->scCfg.nonLinear    = FALSE;
        pScPrm->scCfg.stripSize    = 0;

        pScPrm->userCoeff = FALSE;


        pPortCfg = &pInstPrm->vipPortCfg;
        pPortCfg->syncType          =   SYSTEM_VIP_SYNC_TYPE_DIS_SINGLE_YUV;

        pPortCfg->intfCfg.clipActive    =   FALSE;
        pPortCfg->intfCfg.clipBlank     =   FALSE;
        pPortCfg->intfCfg.intfWidth     =   SYSTEM_VIFW_16BIT;

        pPortCfg->disCfg.fidSkewPostCnt     =   0;
        pPortCfg->disCfg.fidSkewPreCnt      =   0;
        pPortCfg->disCfg.lineCaptureStyle   =   SYSTEM_VIP_LINE_CAPTURE_STYLE_HSYNC;
        pPortCfg->disCfg.fidDetectMode      =   SYSTEM_VIP_FID_DETECT_MODE_VSYNC;
        pPortCfg->disCfg.actvidPol          =   SYSTEM_POL_HIGH;
        pPortCfg->disCfg.vsyncPol           =   SYSTEM_POL_HIGH;
        pPortCfg->disCfg.hsyncPol           =   SYSTEM_POL_HIGH;
        pPortCfg->disCfg.discreteBasicMode  =   FALSE;

        pPortCfg->comCfg.ctrlChanSel        =   SYSTEM_VIP_CTRL_CHAN_SEL_7_0;
        pPortCfg->comCfg.ancChSel8b         =   SYSTEM_VIP_ANC_CH_SEL_8B_LUMA_SIDE;
        pPortCfg->comCfg.pixClkEdgePol      =   SYSTEM_EDGE_POL_RISING;
        pPortCfg->comCfg.invertFidPol       =   FALSE;
        pPortCfg->comCfg.enablePort         =   FALSE;
        pPortCfg->comCfg.expectedNumLines   =   pInprms->height;
        pPortCfg->comCfg.expectedNumPix     =   pInprms->width;
        pPortCfg->comCfg.repackerMode       =   SYSTEM_VIP_REPACK_CBA_TO_CBA;

        pPortCfg->actCropEnable                         =   FALSE;
        pPortCfg->actCropCfg.srcNum                     =   0;
        pPortCfg->actCropCfg.cropCfg.cropStartX         =   0;
        pPortCfg->actCropCfg.cropCfg.cropStartY         =   0;
        pPortCfg->actCropCfg.cropCfg.cropWidth          =   pInprms->width;
        pPortCfg->actCropCfg.cropCfg.cropHeight         =   pInprms->height;

        pPortCfg->ancCropEnable                         =   FALSE;
        pPortCfg->ancCropCfg.srcNum                     =   0;
        pPortCfg->ancCropCfg.cropCfg.cropStartX         =   0;
        pPortCfg->ancCropCfg.cropCfg.cropStartY         =   0;
        pPortCfg->ancCropCfg.cropCfg.cropWidth          =   pInprms->width;
        pPortCfg->ancCropCfg.cropCfg.cropHeight         =   pInprms->height;

        pInstPrm->numBufs = CAPTURE_LINK_NUM_BUFS_PER_CH_DEFAULT;

    }
}

pipeline.c

create(...)
{
    status = System_linkCreate(pObj->IssCaptureLinkID, &pObj->IssCaptureLinkPrm, sizeof(IssCaptureLink_CreateParams));
    UTILS_assert(status == SYSTEM_LINK_STATUS_SOK);

    PlatformUnlockMMR();
    PlatformCAL2VPortConfig(1, TRUE);
    PlatformCAL2VPortConfig(2, TRUE);
    PlatformCAL2VPortConfig(3, TRUE);
    PlatformCAL2VPortConfig(4, TRUE);
    PlatformLockMMR();

    pObj->VipCaptureLinkPrm.callback = &CaptureLink_CB;
    pObj->VipCaptureLinkPrm.appObj = appObj;

    status = System_linkCreate(pObj->VipCaptureLinkID, &pObj->VipCaptureLinkPrm, sizeof(CaptureLink_CreateParams));
    UTILS_assert(status == SYSTEM_LINK_STATUS_SOK);
}

start(..)
{
    status = System_linkStart(pObj->VipCaptureLinkID);
    UTILS_assert(status == SYSTEM_LINK_STATUS_SOK);

    status = System_linkStart(pObj->IssCaptureLinkID);
    UTILS_assert(status == SYSTEM_LINK_STATUS_SOK);

}

0 Sujith over 5 years ago in reply to Vladimir Yakovlev1

TI__Genius 12455 points

Hi Vladmir,

Couple of things to check on this

Ensure that you have setup to transfer 1 pixel per clock on vPort i.e. in function CalSetVportCfg () ensure cfg->width is set to 0
1. Also in the same function check by configuring cfg->xBlk to 0 and cfg->yBlk to 0
Please increase the vPort pixel clock. i.e. drvCalCfg->vportCfg[strmId].pixClock = 32800U; or 36864
Also check if there are any overflow in VIP, i.e. check register VIP_FIQ_STATUS

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Helloб Sujith

I changed params, but as before I don't receive frames. Also I enable extended statistic from VIP driver - please see attached log

cfg->width = 0

cfg->xBlk = 0

cfg->yBlk =0

cfg->pixClock to 32800U for first and 36864U for second

BR, Vladimir

1030.cal2vip_log.txt

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[IPU1-0]     13.248978 s:  CAPTURE: VIP1 Slice0 PortA FRAME MODE
[IPU1-0]     13.249069 s:  CAPTURE: VIP1 Slice1 PortA FRAME MODE
[IPU1-0]     13.249130 s:  CAPTURE: VIP2 Slice0 PortA FRAME MODE
[IPU1-0]     13.249191 s:  CAPTURE: VIP2 Slice1 PortA FRAME MODE
[IPU1-0]     13.249283 s:  
[IPU1-0]     13.249313 s:  [ CAPTURE ] Link Statistics,
[IPU1-0]     13.249374 s:  ******************************
[IPU1-0]     13.249435 s:  
[IPU1-0]     13.249496 s:  Elapsed time       = 3184 msec
[IPU1-0]     13.249557 s:  
[IPU1-0]     13.249588 s:  
[IPU1-0]     13.249649 s:  Input Statistics,
[IPU1-0]     13.249679 s:  
[IPU1-0]     13.249740 s:  CH | In Recv | In Drop | In User Drop | In Process 
[IPU1-0]     13.249801 s:     | FPS     | FPS     | FPS          | FPS        
[IPU1-0]     13.249923 s:  -------------------------------------------------- 
[IPU1-0]     13.250015 s:  
[IPU1-0]     13.250045 s:  Output Statistics,
[IPU1-0]     13.250106 s:  
[IPU1-0]     13.250137 s:  CH | Out | Out     | Out Drop | Out User Drop 
[IPU1-0]     13.250228 s:     | ID  | FPS     | FPS      | FPS           
[IPU1-0]     13.250289 s:  --------------------------------------------- 
[IPU1-0]     13.250533 s:  
[IPU1-0]     13.250564 s:  [VIP1 Slice0 PortA] Statistics
[IPU1-0]     13.250625 s:  ==============================
[IPU1-0]     13.250686 s:  Number of request queued  : 1
[IPU1-0]     13.250777 s:  Number of request dequeued: 0
[IPU1-0]     13.250838 s:  Overflow Count            : 0
[IPU1-0]     13.250930 s:  
[IPU1-0]     13.250960 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.251113 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.251235 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.251570 s:   00.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.251692 s:  
[IPU1-0]     13.251753 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000 
[IPU1-0]     13.251845 s:  
[IPU1-0]     13.251906 s:  [VIP1 Slice1 PortA] Statistics
[IPU1-0]     13.251997 s:  ==============================
[IPU1-0]     13.252058 s:  Number of request queued  : 1
[IPU1-0]     13.252119 s:  Number of request dequeued: 0
[IPU1-0]     13.252180 s:  Overflow Count            : 0
[IPU1-0]     13.252241 s:  
[IPU1-0]     13.252302 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.252424 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.252546 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.252882 s:   02.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.253034 s:  
[IPU1-0]     13.253065 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000 
[IPU1-0]     13.253156 s:  
[IPU1-0]     13.253187 s:  [VIP2 Slice0 PortA] Statistics
[IPU1-0]     13.253248 s:  ==============================
[IPU1-0]     13.253309 s:  Number of request queued  : 1
[IPU1-0]     13.253400 s:  Number of request dequeued: 0
[IPU1-0]     13.253461 s:  Overflow Count            : 0
[IPU1-0]     13.253522 s:  
[IPU1-0]     13.253553 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.253705 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.253827 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.254163 s:   04.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.254285 s:  
[IPU1-0]     13.254346 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000 
[IPU1-0]     13.254437 s:  
[IPU1-0]     13.254468 s:  [VIP2 Slice1 PortA] Statistics
[IPU1-0]     13.254529 s:  ==============================
[IPU1-0]     13.254590 s:  Number of request queued  : 1
[IPU1-0]     13.254681 s:  Number of request dequeued: 0
[IPU1-0]     13.254742 s:  Overflow Count            : 0
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

[IPU1-0]     13.248978 s:  CAPTURE: VIP1 Slice0 PortA FRAME MODE
[IPU1-0]     13.249069 s:  CAPTURE: VIP1 Slice1 PortA FRAME MODE
[IPU1-0]     13.249130 s:  CAPTURE: VIP2 Slice0 PortA FRAME MODE
[IPU1-0]     13.249191 s:  CAPTURE: VIP2 Slice1 PortA FRAME MODE
[IPU1-0]     13.249283 s:  
[IPU1-0]     13.249313 s:  [ CAPTURE ] Link Statistics,
[IPU1-0]     13.249374 s:  ******************************
[IPU1-0]     13.249435 s:  
[IPU1-0]     13.249496 s:  Elapsed time       = 3184 msec
[IPU1-0]     13.249557 s:  
[IPU1-0]     13.249588 s:  
[IPU1-0]     13.249649 s:  Input Statistics,
[IPU1-0]     13.249679 s:  
[IPU1-0]     13.249740 s:  CH | In Recv | In Drop | In User Drop | In Process 
[IPU1-0]     13.249801 s:     | FPS     | FPS     | FPS          | FPS        
[IPU1-0]     13.249923 s:  -------------------------------------------------- 
[IPU1-0]     13.250015 s:  
[IPU1-0]     13.250045 s:  Output Statistics,
[IPU1-0]     13.250106 s:  
[IPU1-0]     13.250137 s:  CH | Out | Out     | Out Drop | Out User Drop 
[IPU1-0]     13.250228 s:     | ID  | FPS     | FPS      | FPS           
[IPU1-0]     13.250289 s:  --------------------------------------------- 
[IPU1-0]     13.250533 s:  
[IPU1-0]     13.250564 s:  [VIP1 Slice0 PortA] Statistics
[IPU1-0]     13.250625 s:  ==============================
[IPU1-0]     13.250686 s:  Number of request queued  : 1
[IPU1-0]     13.250777 s:  Number of request dequeued: 0
[IPU1-0]     13.250838 s:  Overflow Count            : 0
[IPU1-0]     13.250930 s:  
[IPU1-0]     13.250960 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.251113 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.251235 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.251570 s:   00.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.251692 s:  
[IPU1-0]     13.251753 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000 
[IPU1-0]     13.251845 s:  
[IPU1-0]     13.251906 s:  [VIP1 Slice1 PortA] Statistics
[IPU1-0]     13.251997 s:  ==============================
[IPU1-0]     13.252058 s:  Number of request queued  : 1
[IPU1-0]     13.252119 s:  Number of request dequeued: 0
[IPU1-0]     13.252180 s:  Overflow Count            : 0
[IPU1-0]     13.252241 s:  
[IPU1-0]     13.252302 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.252424 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.252546 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.252882 s:   02.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.253034 s:  
[IPU1-0]     13.253065 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000 
[IPU1-0]     13.253156 s:  
[IPU1-0]     13.253187 s:  [VIP2 Slice0 PortA] Statistics
[IPU1-0]     13.253248 s:  ==============================
[IPU1-0]     13.253309 s:  Number of request queued  : 1
[IPU1-0]     13.253400 s:  Number of request dequeued: 0
[IPU1-0]     13.253461 s:  Overflow Count            : 0
[IPU1-0]     13.253522 s:  
[IPU1-0]     13.253553 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.253705 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.253827 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.254163 s:   04.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.254285 s:  
[IPU1-0]     13.254346 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000 
[IPU1-0]     13.254437 s:  
[IPU1-0]     13.254468 s:  [VIP2 Slice1 PortA] Statistics
[IPU1-0]     13.254529 s:  ==============================
[IPU1-0]     13.254590 s:  Number of request queued  : 1
[IPU1-0]     13.254681 s:  Number of request dequeued: 0
[IPU1-0]     13.254742 s:  Overflow Count            : 0
[IPU1-0]     13.254803 s:  
[IPU1-0]     13.254834 s:     CH    |     Q      DQ     Total   Top     Bot    Total  Top    Bot   Min/Max     Min/Max   Dropped  Repeat   Fid   Desc 
[IPU1-0]     13.255017 s:  (I/S/CH) |   Count   Count  Fields  Fields  Fields   FPS   FPS    FPS    Width       Height   Frames   Frames  Repeat Error
[IPU1-0]     13.255169 s:  ---------------------------------------------------------------------------------------------------------------------------
[IPU1-0]     13.255474 s:   06.0.00 |       4       0       0       0       0      0     0     0     0/0         0/0           0       0       0     0
[IPU1-0]     13.255596 s:  
[IPU1-0]     13.255657 s:  CAPTURE: Check VIP_FIQ_STATUS = 0x00000000

0 Sujith over 5 years ago in reply to Vladimir Yakovlev1

TI__Genius 12455 points

Hi Vladmir,

Can you please provide the value of register at 0x489B 0350 and 0x489B 0124

Regards, Sujith

0 Vladimir Yakovlev1 over 5 years ago in reply to Sujith

Prodigy 100 points

Hello Sujith

[IPU1-0] 20.284054 s: Reg 0x489B0350 = 0x0000001B
[IPU1-0] 20.284145 s: Reg 0x489B0124 = 0x00010021

...

[IPU1-0] 26.790032 s: Reg 0x489B0350 = 0x00000079
[IPU1-0] 26.790123 s: Reg 0x489B0124 = 0x00010021

...

[IPU1-0] 38.516714 s: Reg 0x489B0350 = 0x00000122
[IPU1-0] 38.516775 s: Reg 0x489B0124 = 0x00010021

...

[IPU1-0] 187.701030 s: Reg 0x489B0350 = 0x00000985
[IPU1-0] 187.701122 s: Reg 0x489B0124 = 0x00010021

BR, Vladimir

0 BenM over 5 years ago in reply to Vladimir Yakovlev1

Expert 2220 points

Hello,

I am also trying to get this working (with only three cameras). I followed the steps outlined so far and I am not receiving any frames through the VIP

I am receiving counting frames in 0x489b0350

and reg 0x489b0124 = 0x00010021 similar to Vladimir.

Were there any additional steps to get this working?

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hello Ben,

Could you please share the VIP registers? Let check if VIP is receiving some data.

If VIP is not receiving any data, there might be some intermediate mux which is not enabled..

I am trying to figure out mux configuration, could you please share VIP register dump?

Rgds,

Brijesh

0 Brijesh Jadav over 5 years ago in reply to Brijesh Jadav

TI__Guru**** 450155 points

Please also check if the register CTRL_CORE_CONTROL_SPARE_RW(0x4A002E68), bit [12:8] are configured to value 1, as this connects CAL to VIP.

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

VIP1_regs.txt

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XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

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Hello,

I have attached the VIP1 register dump, also register 0x4A002E68 = 0x00001E00. Please let me know if I can provide any other information or if a live debug session would help.

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hi Ben,

VIP parser registers start from offset 0x5500, can you please share 100 regsiters from this offset for VIP0 and VIP2.

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

VIP2_Slice1_parser_regs.txt

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1651 9 48995a00 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

1651 9 48995a00 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
07808000
04380000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

VIP2_Slice0_parser_regs.txt

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1651 9 48995500 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

1651 9 48995500 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
07808000
04380000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

VIP1_Slice1_parser_regs.txt

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1651 9 48975a00 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

1651 9 48975a00 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
07808000
04380000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

VIP1_Slice0_parser_regs.txt

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1651 9 48975500 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
07808000
04380000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

1651 9 48975500 0 64 0
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
07808000
04380000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00403904
07800438
00000000
00000000
003FFEDF
003FFEDF
00000000
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

VIP_regs_all.txt

Hi Brijesh, Sorry I meant to save a longer register dump. Please let me know if you need any additional registers

0 BenM over 5 years ago in reply to BenM

Expert 2220 points

VIP3_Slice1_parser_regs.txt

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1651 9 489b5a00 0 64 0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

1651 9 489b5a00 0 64 0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

VIP3_Slice0_parser_regs.txt

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1651 9 489b5500 0 64 0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

1651 9 489b5500 0 64 0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Ben,

None of the VIP ports are enabled. Are you sure you are using correct VIP?

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Hi Brijesh,

Are you referring to VIP_PORT_A.ENABLE (bit 8)? I see it as being set to 0x00403904 which would be enabled? Are you referring to a different register?

I realized after the fact that there is no VIP3 in TDA2Px, so those registers are all zero.

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hi Ben,

Yes, i was looking for ENABLE bit.

the Parser registers are at the offset 0x5500 and 0x5A00. At these offsets, ENABLE bit is not set.

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Brijesh,

I'm sorry if I am not understanding. Looking at the TDA2P TRM offset 48975500 is the VIP_MAIN register which has the following fields:

31:6 RESERVED

5 CLIP_ACTIVE

4 CLIP_BLINK

3:2 RESERVED

1:0 DATA_INTERFACE_MODE

I do not see an enable bit in this register. However, the next register, 0x4897 5504 bit 8 contains an ENABLE field and this bit is being set in the register dumps that I have provided.

If this is not the bit you are talking about please specify the exact bit that you are looking for to be set, because I am not understanding.

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hi Ben,

Please find base picture giving base address of VIP registers. VIP_PORT_A/B register have enable bit, which must be enabled to get VIP working.

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Brijesh,

As you can see in the register dumps provided earlier:

1651 9 48975500 0 64 0
00000001
00403904 <-VIP1 Slice 0 VIP_PORT_A bit 8 is set, it is ENABLED
07800438

1651 9 48975a00 0 64 0
00000001
00403904 <-VIP1 Slice 1 VIP_PORT_A bit 8 is set, it is ENABLED
07800438

1651 9 48995500 0 64 0
00000001
00403904 <-VIP2 Slice 0 VIP_PORT_A bit 8 is set, it is ENABLED
07800438

1651 9 48995a00 0 64 0
00000001
00403904 <-VIP2 Slice 1 VIP_PORT_A bit 8 is set, it is ENABLED
07800438

Are you saying that VIP_PORT_B needs to be enabled? These ports do not support 16 bits, so I was under the impression that the A ports must be used. I appreciate your clarification.

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Ben,

oh ok, config seems to be correct, let me look at reference implementation and get back to you.

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Any update on this topic? It is becoming a blocking issue for our customer.

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hi Ben,

Can you please check if

1, bits [12:9] are set to 1'b in the register CTRL_CORE_CONTROL_SPARE_RW (0x4A002E68)

2, Bit 31 is set to 0'b in the register CTRL_CORE_SMA_SW_3 (0x4A003C08)

Regards,

Brijesh

0 Brijesh Jadav over 5 years ago in reply to Brijesh Jadav

TI__Guru**** 450155 points

Also Can you please check if CAL Write DMA is enabled, you are able to capture the frames? I means if VP is not enabled, then CAL is able to detect the input stream and is able to capture the frames??

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Hi Brijesh,

I enabled writeToMem:

drvCalCfg->writeToMem[strmId] = (UInt32)TRUE;

and am seeing 1080p60 capture on all three streams.

CTRL_CORE_CONTROL_SPARE_RW (0x4A002E68) = 0x00001E00

CTRL_CORE_SMA_SW_3 (0x4A003C08) = 0x00000001

For a 1080p60 yuv422 stream, what should drvCalCfg->vportCfg[i].pixClock be set to?

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hi Ben,

I am setting below config for VPORT, could you please try it?

CAL_VPORT_CTRL1 = 0x00050000;

CAL_VPORT_CTRL2 = 0x00008020;

Rgds,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Hi Brijesh,

Thank you for continuing to look into this.

I have set mine to match what you have and am still not seeing anything. Can I provide any other information to you? Please let me know if a live debug session would be helpful.

Thanks,

Ben

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Hi Ben,

This has never been tried/tested on EVM, with actual sensor. So is taking time.

We can have debug session, but i doubt how much it will be helpful.

Lets first make sure that the CAL is able to transfer data. There is a IRQ_VPORT_EOF event, which gets generated when Vport sends last pixel. Are you seeing this event? If you are seeing this event, then atleast, CAL is transmitting the frames.

Now if the VIP is not receiving frames, something in between is not allowing signals to pass. Let me again go through TRM and check if we is missing anything..

Regards,

Brijesh

0 BenM over 5 years ago in reply to Brijesh Jadav

Expert 2220 points

Thank you for the debug session.

The final changes needed to get this working was:

CAL_VPORT_CTRL2 = 0x10021

pInstPrm->videoIfMode = SYSTEM_VIFM_SCH_DS_AVID_VSYNC;

pPortCfg->disCfg.lineCaptureStyle =
SYSTEM_VIP_LINE_CAPTURE_STYLE_ACTVID;

0 Brijesh Jadav over 5 years ago in reply to BenM

TI__Guru**** 450155 points

Thanks Ben, i am closing this thread.

Processors

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TDA2PXEVM: Provide frames from CSI(CAL) to VIP on the fly