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TMS320C6657: Question about C6657 DDR ECC function.

Denny%20Yang99373
Expert 3805 points
Part Number: TMS320C6657


Hi all,

I have a questions:

1, How use the DDR ecc fuction? After DDR ecc enabled, it must read/write DDR by 64bit aligned. How control this, In my option we should enable L2 cache, L2 cache will maintenance the cache line 64bit align. This will can meet the DDR ECC 64bit align requirement.
Are  there any other suggestion for this?

2, After I enable DDR ECC and enable L2 cache, used below test code. After CACHE_wbInvL2(), the exception Event 110 happened.
I want to know why it will trigger event 110? The DDR_ECC_Test address is 0x88000000, well aligned.

thanks!

BR,

Denny

code like below:

puts("make the test data space cacheable");
gpCGEM_regs->MAR[((Uint32)DDR_ECC_Test)/(16*1024*1024)]=1;
#if 1
//clear the ECC errot status
gpDDR_regs->IRQSTATUS_SYS= CSL_EMIF4F_IRQSTATUS_SYS_REG_RD_ECC_ERR_SYS_MASK
|CSL_EMIF4F_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_MASK;

printf("Fill (STDW, 64-bit aligned) test buffer from 0x%x with 0 ...\n", DDR_ECC_Test);

/*memset is implemented with STDW (64-bit aligned). Since L2 cache is enabled,
data line will be read into cache, and then new data will be written in the cache*/
memset((void *)DDR_ECC_Test, 0x59, 128);

puts("!!!CACHE_wbInvL2 on the test data buffer, a spurious write ECC error and MDMA error will be generated, these should be ignored in real application...");
CACHE_wbInvL2((void *)DDR_ECC_Test, 128, CACHE_NOWAIT);
/*normally, exception is captured about 10~100 cycles after the
access violation. Dummy operations added here to wait for it.*/
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5");
asm(" nop 5"); /*NRP should be around the address of this instruction*/
asm(" nop 5");
_mfence();
_mfence();

  • 0
    TI__Guru* 95265 points

    Hi Denny,

    1. You can enable L1D and L2 cache, then accessing the DDR3 at 64-bit aligned. 

    2. For DDR3 ECC testing, there were some past queries about it. All TI 6678 and 6657 EVMs are not assembled with an additional DDR3 chip for ECC purpose:  https://e2e.ti.com/support/processors/f/791/t/571189. So there is no way to test it using TI EVM. There is no TI official test code for DDR ECC test.

    3. There are a code using GEL discussed here: https://e2e.ti.com/support/processors/f/791/p/590958/2171758

    4. Some customers used the STK V 1.1 code for this purpose, as you did. I look at the code, there is EDMA fill in the test region with all 0 EDMA_fill((Uint32)DDR_ECC_Test, 0, DDR_ECC_TEST_BUF_SIZE_BYTES, EDMA_CC0_CH0);

    I don't understand below code:

    /*memset is implemented with STDW (64-bit aligned). Since L2 cache is enabled,
    data line will be read into cache, and then new data will be written in the cache*/
    memset((void *)DDR_ECC_Test, 0, 128);

    puts("!!!CACHE_wbInvL2 on the test data buffer, a spurious write ECC error and MDMA error will be generated, these should be ignored in real application...");
    CACHE_wbInvL2((void *)DDR_ECC_Test, 128, CACHE_NOWAIT);

    Why need to do a 128 bytes write? and it seems that MDMA error (110) is a known issue from the comments? And in the STK code, you enabled DDR ECC by calling KeyStone_DDR_init() for C6657, correct? 

    Please try to use    *(unsigned char*)(0x8800_0001) = 0x01 or 0x3; to see if you can create a 1-bit or 2-bit ECC error?

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    Also there is an application note explained DDR3 test in Section 3.4, it explained how DDR3 ECC was tested at that time.

    3113.Build Robust System on KeyStone Devices.pdf

    Regards, Eric