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Original question:

[IPC][SYS/BIOS]Questions about IPC on TDA4

[TDA4][IPC]How to set the other part of DDR as cached on C66, meanwhile ipc/VRing buffer uncached?

lance
Intellectual 500 points

If I set MAR as below，I can use IPC to communicate with Linux A72.

But if I set MAR as following, Linux will not find char device "rpmsg_chrdev", so that I can not communicate with Linux A72

  • 0
    TI__Genius 9101 points

    See vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/c66x_1/main.c, appCacheMarInit

        /* enable cache for cached sections */
        Cache_setMar((Ptr)DDR_C66x_1_DTS_ADDR, DDR_C66x_1_DTS_SIZE, Cache_Mar_ENABLE);
        Cache_setMar((Ptr)DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_SIZE, Cache_Mar_ENABLE);

        /* disable cache for non-cached sections */
        Cache_setMar((Ptr)DDR_C66x_1_IPC_ADDR, DDR_C66x_1_IPC_SIZE, Cache_Mar_DISABLE);
        Cache_setMar((Ptr)APP_LOG_MEM_ADDR, APP_LOG_MEM_SIZE, Cache_Mar_DISABLE);
        Cache_setMar((Ptr)TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_SIZE, Cache_Mar_DISABLE);
        Cache_setMar((Ptr)IPC_VRING_MEM_ADDR, IPC_VRING_MEM_SIZE, Cache_Mar_DISABLE);

    Mar_ENABLE enables cache for these regions.

    Mar_DISABLE disables cache for these regions.

    Note, the below contraints though,

    - region start address MUST be 16MB aligned

    - region size MUST be 16MB aligned.

    i.e you can enable or disable cache in units of 16MB

    regards

    Kedar