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Original question:

J721E ddr bist

DRA829V: DDR ECC cache line

Ryan Stark
Expert 2930 points
Part Number: DRA829V


I have a few questions about the ddr ecc cache.

1)Where is route id used in DDRSS_ECC_RID_VAL_REG defined? I see values like 0x69 used for DRU in j7_ddr_config.gel but don't know where it comes from. I was expecting it in Table 3-23 but dont think that is correct.

2)Using DRU to memset memory to 0 I see these benchmark numbers when allocating cache lines to 0x8069. I had WR_ALLOC bit set but it didn't seem to matter.

a)no entries aka all DDRSS_ECC_RID_VAL_REG = 0. 10.2gby/s

b)1 entry 5.8gyb/s. When you hard code a cache line does that mean that route id will not use any of the other unallocated ones?

c)8 entries 11.1gby/s. Why is it better to only have 8 vs 64? 

d)64 entries 10.6 gby/s. 

e)9 entries allocated to 0x8068(any non dru route id works here)  and others all 0.  6.6gby/sec. Why when only allocating a few cache lines to a different route id does it affect other master performance so much?

  • 0
    TI__Mastermind 40330 points

    Hi,

    We will look into your questions.

    Best regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Mastermind 40330 points

    Hi,

    For #1, Table 3-23 through Table 3-36 appears to have some of the RouteIDs, but is not the full list. It does not appear 0x68 or 0x69 are currently published in the TRM; however, these should correspond to the DRU. Still trying to follow-up on differences between the two RouteIDs.

    For #2, the following comments per configuration were received from the design team. Let us know if this doesn't answer your questions.

    a) No entries allocated means that the entire cache will use all unallocated entries for that master (similar to all entries) See d below

    b) Uses a single entry so any reordering via MSMC will cause write backs.

    c) 4 is optimal for MSMC, and 8 looks just as good, the write backs are near enough so the banks are still open.

    d) 64 entries, similar to ‘a’ above where there are so many that the row is probably being closed, so it needs to be reopened for the ECC evict causing bank thrashing.

    e) If you set all entries to something, one entry will be flipped back to unallocated and used for all operations

    The ECC cache is a 128 way cache where each way can be allocated to particular route IDs. if all route ID are allocated, one will be flipped back to be used by all unallocated route IDs. Because the ECC is stored near the data the more cache lines associated with a master, the higher probability the ECC evict will cause a bank to be re-opened. At the same time, the MSMC will reorder due to its banking, so if you have less than 4 then there is a probability that MSMC reordering can cause bank thrashing as well.

  • 0 in reply to Kevin S
    Expert 2930 points

    Thanks

    1)Let me know when all route ids are published

    2 e) I am not sure I understand the answer. I only had 9 allocated to a different route id and the rest were 0(unallocated) and it cut my bandwidth to almost 1/2.

    3) How does it find a cache line? Is it least recently used, round robin,..

  • 0 in reply to Ryan Stark
    TI__Mastermind 40330 points

    Hi Ryan,

    Sorry for the delay.

    For #2, to clarify, were the other entries set to 0x8000 or 0x0000? If  0x0000, then all but the 9 entries would be used for route ID 0x69. 

    For #3, the cache is LRU (lease recently used). All unallocated entries are available for all masters that are not specified in the allocation table.