• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 2151 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM：TDA4 - Enable MCU R5F lock step mode

chun chu1
Intellectual 330 points
Part Number: TDA4VM


Hi experts,

How to enable MCU R5F lock step mode?

I found in TRM that the LOCKSTEP of the CTRLMMR_MCUSEC_CLSTR0_CFG register needs to be set, but the API for setting this register was not found in the SDK. And need to call CSL_armR5CCMSetOperationModeKey () to set the operation mode.

Please provide the steps to enable MCU R5F lock step mode and where to call these APIs.

Regards,

ChunChu

  • 0
    TI__Mastermind 30245 points

    ChunChu

    Apologies on the delay in response on this one. 

    The R5F can be configured to lockstep from software using the System Firmware APIs.

    You can see an example for this in pdk/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c

    Function: SBL_ConfigMcuLockStep

    Description of the API is as given here: http://software-dl.ti.com/tisci/esd/19_08_00/2_tisci_msgs/security/PROC_BOOT.html

    Thanks and Regards

    Piyali

  • 0 in reply to Piyali Goswami
    Intellectual 330 points

    Hi Piyali,

    Thanks for your reply.

    I checked SBL_ConfigMcuLockStep (). Do we have to set core_id to MCU1_SMP_ID to enable lock step mode of MCU1_CPU0_ID?

    How to confirm that MCU1_CPU0 has successfully turned on the lock step mode?

    Regards,

    ChunChu

  • 0 in reply to chun chu1
    TI__Mastermind 30245 points

    Hi ChunChu

    If you are using /pdk/packages/ti/boot/sbl/tools/scripts/K3ImageGen.sh, yes you would need to set MCU1_SMP_ID for the application image.

    You should be able to see the CTRLMMR_MCUSEC_CLSTR0_CFG bit 0 set to 1 when the R5Fs are in lock step.

    Thanks and Regards

    Piyali

  • 0 in reply to Piyali Goswami
    Intellectual 330 points

    Hi Piyali,

    1. I have turned on MCU1_CPU0 lockstep mode and read the CTRLMMR_MCUSEC_CLSTR0_CFG->LOCKSTEP to 1 in the adc_app example of MCU1_CPU0. But CCMSR1->CMPE1 is always 0x1: CPU signal compare mismatch, why is it? (Lockstep operation mode is 0x0: active compare lockstep mode)

    2. Can I only check CCMSR1 status by polling? Is there a way to trigger the compare error in CCMSR1 via an interrupt?

    Regards,

    ChunChu

  • 0 in reply to chun chu1
    TI__Mastermind 30245 points

    Hi ChunChu

    Are you rebooting the R5F subsystem after writing to the lockstep bit? If not, you would need to do that to enter into lockstep mode. Please have a look at the sequence in pdk/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c

    Function: SBL_ConfigMcuLockStep

    Thanks and Regards

    Piyali

  • 0 in reply to Piyali Goswami
    Intellectual 330 points

    Hi Piyali,

    SDK:6.1.0
    I boot the adc_app example of MCU1_CPU0 with SD card in pdk / packages / ti / boot / sbl / board / k3 / sbl_main.c.
    Function: SBL_ImageCopy

    As you said, before calling SBL_ConfigMcuLockStep (), need to call SBL_SetupCoreMem (), and enable MCU1_CPU0_ID lockstep mode by entering core_id = MCU1_SMP_ID, but I do n’t know how to make the input parameter of SBL_SetupCoreMem () to MCU1_SMP_ID

    At present, my method is to set the runLockStep function in SBL_SetupCoreMem () to 1 to start the MCU1_CPU0_ID lockstep mode. If the above method is wrong, how can I correctly start the MCU1_CPU0_ID lockstep mode?

    Regards,

    ChunChu

  • 0 in reply to chun chu1
    Intellectual 330 points

    Hi Piyali,

    I have made new progress,
    As mentioned above, in the adc_app example, CCMSR1-> CMPE1 is always 0x1.
    -->The issue is that I did not clear the comparison error signal (CCMSR1-> CMPE1) in the adc_app example. After starting the APP, clear CCMSR1-> CMPE1 once, I will no longer see CCMSR1-> CMPE1 as 0x1.

    But I have another question, I hope you can answer it:
    Is there a way to trigger the compare error(CMPE1) in CCMSR1 via an interrupt? (I am polling in the adc_app example to check the status of CCMSR1, but this is too slow, which will prevent me from getting the status of the "Error Forcing Mode" and "Self Test Error Forcing Mode".)

    Regards,

    ChunChu

  • 0 in reply to chun chu1
    TI__Mastermind 30245 points

    Hi Chun Chu

    The compare error signal which corresponds to this bit is routed to the ESM. You can use the MCU_MCU0_CCM_STAT_ERR_INT signal to the ESM and then generate the interrupt from the ESM.

    A generic ESM example is given in pdk\packages\ti\csl\example\esm\esm_clk_loss_test_app

    Thanks and Regards

    Piyali