66AK2H14: DDR3 configuration problem

Part Number: 66AK2H14

K2_DDR3_Register_Calc_v1p60_AS4C512M16D3L-12BIN_V1.xlsx

arm_A15_0: GEL Output: GEL file Ver is 1.89999998 
arm_A15_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000
arm_A15_0: GEL Output: (3a) PLLCTL = 0x00000040
arm_A15_0: GEL Output: (3b) PLLCTL = 0x00000040
arm_A15_0: GEL Output: (3c) Delay...
arm_A15_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
arm_A15_0: GEL Output: MAINPLLCTL0 = 0x38000C1F
arm_A15_0: GEL Output: (5) MAINPLLCTL0 = 0x07000C1F
arm_A15_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
arm_A15_0: GEL Output: (6) MAINPLLCTL0 = 0x07000C00
arm_A15_0: GEL Output: (7) SECCTL = 0x00090000
arm_A15_0: GEL Output: (8a) Delay...
arm_A15_0: GEL Output: PLL1_DIV3 = 0x00008002
arm_A15_0: GEL Output: PLL1_DIV4 = 0x00008004
arm_A15_0: GEL Output: PLL1_DIV7 = 0x00000000
arm_A15_0: GEL Output: (8d/e) Delay...
arm_A15_0: GEL Output: (10) Delay...
arm_A15_0: GEL Output: (12) Delay...
arm_A15_0: GEL Output: (13) SECCTL = 0x00090000
arm_A15_0: GEL Output: (Delay...
arm_A15_0: GEL Output: (Delay...
arm_A15_0: GEL Output: (14) PLLCTL = 0x00000041
arm_A15_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
arm_A15_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz)
arm_A15_0: GEL Output: Switching on ARM Core 0
arm_A15_0: GEL Output: Switching on ARM Core 1
arm_A15_0: GEL Output: Switching on ARM Core 2
arm_A15_0: GEL Output: Switching on ARM Core 3
arm_A15_0: GEL Output: ARM PLL has been configured (100.0 MHz * 28 / 2 = 1400.0 MHz)
arm_A15_0: GEL Output: Set_Psc_All_On begin
arm_A15_0: GEL Output: REG_FIELD ---> 0x000007FF 
arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... 
arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... Done.
arm_A15_0: GEL Output: Set_Psc_All_On end
arm_A15_0: GEL Output: Completed PA PLL Setup
arm_A15_0: GEL Output: PAPLLCTL0 - before: 0x0x070803C0	 after: 0x0x09080500
arm_A15_0: GEL Output: PAPLLCTL1 - before: 0x0x00002040	 after: 0x0x00002040
arm_A15_0: GEL Output: DDR begin
arm_A15_0: GEL Output: XMC setup complete.
arm_A15_0: GEL Output: DDR3 PLL Setup ... 
arm_A15_0: GEL Output: DDR3APLLCTL0 begin = 0x0x071803C0.
arm_A15_0: GEL Output: DDR3APLLCTL1 begin = 0x0x00000040.
arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 800 MHz.
arm_A15_0: GEL Output: DDR3APLLCTL0 end = 0x0x071803C0.
arm_A15_0: GEL Output: DDR3APLLCTL1 end = 0x0x00000040.
arm_A15_0: GEL Output: DDR3A_PGCR1 = 0x0x0280C525.
arm_A15_0: GEL Output: DDR3A_DCR = 0x0x0000040B.
arm_A15_0: GEL Output: DDR3A_DX2GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A_DX3GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A_DX4GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A_DX5GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A_DX6GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A_DX7GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A_DX8GCR = 0x0x7C000E81.
arm_A15_0: GEL Output: DDR3A initialization complete 
arm_A15_0: GEL Output: DDR done
arm_A15_0: GEL Output: Entering A15 non secure mode .. 
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabling SMP bit in ACTLR
arm_A15_0: GEL Output: Enabled SMP bit in ACTLR
arm_A15_0: GEL Output: Entering NonSecure Mode
arm_A15_0: GEL Output: Entered NonSecure Mode
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: A15 non secure mode entered 
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: DDR PLL Registers:

arm_A15_0: GEL Output:  DDR3A_PLL_CTL0 register:  0x071803C0 (0x02620360)
arm_A15_0: GEL Output:  	PLLD[5:0]:		0 (Pre-Divide value of 1)
arm_A15_0: GEL Output:  	PLLM[18:6]:		15 (Multiplier value of 16)
arm_A15_0: GEL Output:  	CLKOD[22:19]:		3 (Output Divide value of 4)
arm_A15_0: GEL Output:  	BYPASS[23]:		0
arm_A15_0: GEL Output:  	BWADJ-lower[31:24]: 	7
arm_A15_0: GEL Output:  DDR3A_PLL_CTL1 register:  0x00000040
arm_A15_0: GEL Output:  	PLLRESET[14]: Reset ** DEASSERTED ** to PLL
arm_A15_0: GEL Output:  	ENSAT[6]: ENSAT is SET - (GOOD)
arm_A15_0: GEL Output:  	BWADJ-upper[3:0]:	0
arm_A15_0: GEL Output:  	BWADJ[11:0] (combined):	7
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: DDR SDRAM Configuration Register (SDCFG)
arm_A15_0: GEL Output: DDR3AEMIF_SDCFG:			0x6200CE62 (Address: 0x21010008)
arm_A15_0: GEL Output: 	SDRAM Type[31:29]:   		DDR3 (3)
arm_A15_0: GEL Output: 	SDRAM Drive[27:25]:  		RZQ/4 (1)
arm_A15_0: GEL Output: 	Dynamic ODT[23:22]:  		OFF (0)
arm_A15_0: GEL Output: 	CAS Write Latency[16:14]:	8 (3)
arm_A15_0: GEL Output: 	Data Bus Width[13:12]: 		64-bit (0)
arm_A15_0: GEL Output: 	CAS Latency[11:8]:		11 (14)
arm_A15_0: GEL Output: 	Banks per SDRAM[6:5]: 		8 (3)
arm_A15_0: GEL Output: 	Chip Select Setup[3]: 		DCE0# (0)
arm_A15_0: GEL Output: 	Page Size[1:0]:    		1024 word page (2)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: SDRAM Refresh Control Register (SDRFC)
arm_A15_0: GEL Output: DDR3AEMIF_SDRFC:			0x00001869 (Address: 0x21010010)
arm_A15_0: GEL Output: 	INITREF_DIS[31]:		Normal operation
arm_A15_0: GEL Output: 	REFRESH_RATE[15:0]:		6249 (REFRESH_RATE = Refresh period * DDR3 clock frequency.)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: SDRAM Timing 1 Register (SDTIM1)
arm_A15_0: GEL Output: DDR3AEMIF_SDTIM1:			0x166C9875 (Address: 0x21010018)
arm_A15_0: GEL Output: 	T_WR[29:25]:			11 cycles (+1)
arm_A15_0: GEL Output: 	T_RAS[24:18]:			27 cycles (+1)
arm_A15_0: GEL Output: 	T_RC[17:10]:			38 cycles (+1)
arm_A15_0: GEL Output: 	T_RRD[9:4]:			7 cycles (+1)
arm_A15_0: GEL Output: 	T_WTR[3:0]:			5 cycles (+1)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: SDRAM Timing 2 Register (SDTIM2)
arm_A15_0: GEL Output: DDR3AEMIF_SDTIM2:			0x00001D4A (Address: 0x2101001C)
arm_A15_0: GEL Output: 	T_RTW[12:10]:			7 cycles (+1)
arm_A15_0: GEL Output: 	T_RP[9:5]:			10 cycles (+1)
arm_A15_0: GEL Output: 	T_RCD[4:0]:			10 cycles (+1)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: SDRAM Timing 3 Register (SDTIM3)
arm_A15_0: GEL Output: DDR3AEMIF_SDTIM3:			0x447DFF53 (Address: 0x21010020)
arm_A15_0: GEL Output: 	T_XP[31:28]:			4 cycles (+1)
arm_A15_0: GEL Output: 	T_XSNR[27:18]:			287 cycles (+1)
arm_A15_0: GEL Output: 	T_XSRD[17:8]:			511 cycles (+1)
arm_A15_0: GEL Output: 	T_RTP[7:4]:			5 cycles (+1)
arm_A15_0: GEL Output: 	T_CKE[3:0]:			3 cycles (+1)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: SDRAM Timing 4 Register (SDTIM4)
arm_A15_0: GEL Output: 	DDR3AEMIF_SDTIM4:		0x543F117F (Address: 0x21010028)
arm_A15_0: GEL Output: 	T_CSTA[31:28]:			4 cycles (+1)
arm_A15_0: GEL Output: 	T_CKESR[27:24]:			4 cycles (+1)
arm_A15_0: GEL Output: 	ZQ_ZQCS[23:16]:			125 cycles (+1)
arm_A15_0: GEL Output: 	T_RFC[13:4]:			1013 cycles (+1)
arm_A15_0: GEL Output: 	T_RAS_MAX[3:0]:(should be 0xF)	3 cycles
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: SDRAM Output Impedance Calibration Configuration Register (ZQCFG)
arm_A15_0: GEL Output: 	DDR3AEMIF_ZQCFG:		0x70074C1F (Address: 0x210100C8)
arm_A15_0: GEL Output: 	ZQ_CS1EN[31]:			ZQ calibration for Rank 2 is Disabled (0)
arm_A15_0: GEL Output: 	ZQ_CS0EN[31]:			ZQ calibration for Rank 1 is Enabled (1)
arm_A15_0: GEL Output: 	ZQ_DUALCALEN[29]:		Dual ZQ calibration is Enabled (1)
arm_A15_0: GEL Output: 	ZQ_SFEXITEN[28]:		ZQ calibration on self-refresh, Active power-down and precharge power-down exit is Enabled (1)
arm_A15_0: GEL Output: 	ZQ_ZQCL_MULT[18:16]:		7 cycles
arm_A15_0: GEL Output: 	ZQ_REFINTERVAL[15:0]:		Refresh periods between ZQCS commands is 19487 (+1)
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: ****************************************************************************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: PLL Control Register (PLLCR)
arm_A15_0: GEL Output: DDR3A_PLLCR:			0x0001C000 (Address: 0x02329018)
arm_A15_0: GEL Output: 	FRQSEL[19:18]:			PLL Reference clock ranges from 335MHz to 533MHz (0)
arm_A15_0: GEL Output: Note: PLL Reference Clock should be 1/4 of DDR data rate. (i.e. 400MHz -> 1600MTs)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: DRAM Timing Parameters Register 0 (DTPR0)
arm_A15_0: GEL Output: DDR3A_DTPR0:			0x9D9CBB66 (Address: 0x02329048)
arm_A15_0: GEL Output: 	tRFC[31:26]:			Activate to Activate command delay (same bank) is 39 cycles
arm_A15_0: GEL Output: 	tRRD[25:22]:			Activate to Activate command delay (diff banks) is 6 cycles
arm_A15_0: GEL Output: 	tRAS[21:16]:			Activate to Precharge command delay is 28 cycles
arm_A15_0: GEL Output: 	tRCD[15:12]:			Activate to Read/Write (on activated row) command delay is 11 cycles
arm_A15_0: GEL Output: 	tRP[11:8]:			Precharge command period is 11 cycles
arm_A15_0: GEL Output: 	tWTR[7:4]:			Internal write to read command delay is 6 cycles
arm_A15_0: GEL Output: 	tRTP[3:0]:			Internal read to precharge command delay is 6 cycles
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: DRAM Timing Parameters Register 1 (DTPR1)
arm_A15_0: GEL Output: DDR3A_DTPR1:			0x3288C400 (Address: 0x0232904C)
arm_A15_0: GEL Output: 	tWLO[29:26]:			Write leveling output delay is 12 cycles
arm_A15_0: GEL Output: 	tWLMRD[25:20]:			Min delay from write leveling mode to first DQS edge is 40 cycles
arm_A15_0: GEL Output: 	tRFC[19:11]:			Refresh to Refresh command delay is 280 cycles
arm_A15_0: GEL Output: 	tFAW[10:5]:			4-bank activate period is 32 cycles
arm_A15_0: GEL Output: 	tMOD[4:2]:			Load mode update delay is 12 cycles (0)
arm_A15_0: GEL Output: 	tMRD[1:0]:			Load mode cycle time is 0 cycles
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: DRAM Timing Parameters Register 2 (DTPR2)
arm_A15_0: GEL Output: DDR3A_DTPR2:			0x5002D200 (Address: 0x02329050)
arm_A15_0: GEL Output: 	tCCD[31]:			Read to read and write to write command delay is 4 cycles (0)
arm_A15_0: GEL Output: 	tRTW[30]:			Read to write command delay is standard bus turn around delay +1 clock (1)
arm_A15_0: GEL Output: 	tRTODT[29]:			Read to ODT delay is 0, may come immediately after read post-amble (0)
arm_A15_0: GEL Output: 	tDLLK[28:19]:			DLL locking time is 512 cycles
arm_A15_0: GEL Output: 	tCKE[28:19]:			CKE minimum pulse width (tCKESR) is 5 cycles
arm_A15_0: GEL Output: 	tXP[14:10]:			Power down exit delay is 20 cycles
arm_A15_0: GEL Output: 	tXS[9:0]:			Self refresh exit delay is 512 cycles
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Mode Register 0 (MR0)
arm_A15_0: GEL Output: DDR3A_MR0:				0x00001C70 (Address: 0x02329054)
arm_A15_0: GEL Output: 	PD[12]:				Fast power down exit (DLL on) (1)
arm_A15_0: GEL Output: 	WR[11:9]:			Write Recovery is 12 cycles (6)
arm_A15_0: GEL Output: 	CL[6:4,2]:			11 cycles (14)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Mode Register 1 (MR1)
arm_A15_0: GEL Output: DDR3A_MR1:				0x00000006 (Address: 0x02329058)
arm_A15_0: GEL Output: 	AL[4:3]:			AL Disabled (0)
arm_A15_0: GEL Output: 	RTT[9,6,2]:			ODT is RZQ/4 on SDRAM (1)
arm_A15_0: GEL Output: 	DIC[5,1]:			Output Drive is RZQ/7 on SDRAM (1)
arm_A15_0: GEL Output: 	DE[0]:				DLL Enabled on SDRAM (0)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Mode Register 2 (MR2)
arm_A15_0: GEL Output: DDR3A_MR2:				0x00000018 (Address: 0x0232905C)
arm_A15_0: GEL Output: 	RTTWR[10:9]:			Dynamic ODT is Disabled (0)
arm_A15_0: GEL Output: 	CWL[5:3]:			CAS Write Latency is 8 cycles (3)
arm_A15_0: GEL Output: 	SRT[7]:				Normal Operating Temperature Range (0)
arm_A15_0: GEL Output: 	ASR[6]:				Auto Self-Refresh Power Management Disabled (0)
arm_A15_0: GEL Output: 	PASR[2:0]:			Partial Array Self-Refresh is set to Full Array (0)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Impedance Control Register 1 (Address/Command/Control signals) (ZQ0CR1)
arm_A15_0: GEL Output: DDR3A_ZQ0CR1:			0x0001005D (Address: 0x02329184)
arm_A15_0: GEL Output: 	ZPROG-ODT[7:4]:			On-Die Termination is set to N/A (5)
arm_A15_0: GEL Output: 	ZPROG-ZO[3:0]:			Output Impedance is set to 34ohms (13)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Impedance Control Register 1 (Data Lanes 0-3) (ZQ1CR1)
arm_A15_0: GEL Output: DDR3A_ZQ1CR1:			0x0001005B (Address: 0x02329194)
arm_A15_0: GEL Output: 	ZPROG-ODT[7:4]:			On-Die Termination is set to 60ohms (5)
arm_A15_0: GEL Output: 	ZPROG-ZO[3:0]:			Output Impedance is set to 40ohms (11)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Impedance Control Register 1 (Data Lanes 4-7) (ZQ2CR1)
arm_A15_0: GEL Output: DDR3A_ZQ2CR1:			0x0001005B (Address: 0x023291A4)
arm_A15_0: GEL Output: 	ZPROG-ODT[7:4]:			On-Die Termination is set to 60ohms (5)
arm_A15_0: GEL Output: 	ZPROG-ZO[3:0]:			Output Impedance is set to 40ohms (11)
arm_A15_0: GEL Output: ********************************************************

arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ***************** DDR3A Leveling Errors *********************
arm_A15_0: GEL Output:  PGSR0[27]:	WEERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[26]:	REERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[25]:	WDERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[24]:	RDERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[23]:	WLAERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[22]:	QSGERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[21]:	WLERR has 	** No Error **
arm_A15_0: GEL Output:  PGSR0[20]:	ZCERR has 	** No Error **

arm_A15_0: GEL Output:  PGSR0[11]:	WEDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[10]:	REDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[9]:		WDDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[8]:		RDDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[7]:		WLADONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[6]:		QSGDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[5]:		WLDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[4]:		DIDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[3]:		ZCDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[2]:		DCDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[1]:		PLDONE is 	** Set **
arm_A15_0: GEL Output:  PGSR0[0]:		IDONE is 	** Set **

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Leveling Errors by Byte Lane:

arm_A15_0: GEL Output: Byte Lane 0: DX0GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX0GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX0GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX0GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX0GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX0GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX0GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX0GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 1: DX1GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX1GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX1GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX1GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX1GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX1GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX1GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX1GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 2: DX2GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX2GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX2GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX2GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX2GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX2GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX2GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX2GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 3: DX3GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX3GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX3GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX3GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX3GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX3GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX3GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX3GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 4: DX4GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX4GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX4GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX4GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX4GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX4GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX4GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX4GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 5: DX5GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX5GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX5GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX5GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX5GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX5GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX5GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX5GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 6: DX6GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX6GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX6GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX6GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX6GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX6GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX6GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX6GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 7: DX7GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX7GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX7GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX7GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX7GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX7GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX7GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX7GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: Byte Lane 8: DX8GSR2 = 0x00000088
arm_A15_0: GEL Output: 	DX8GSR2[6]:   WEERR has 		** No Error **
arm_A15_0: GEL Output: 	DX8GSR2[4]:   REERR has 		** No Error **
arm_A15_0: GEL Output: 	DX8GSR2[2]:   WDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX8GSR2[0]:   RDERR has 		** No Error **
arm_A15_0: GEL Output: 	DX8GSR0[25]:   QSGERR on Rank1 has 	** No Error **
arm_A15_0: GEL Output: 	DX8GSR0[24]:   QSGERR on Rank0 has 	** No Error **
arm_A15_0: GEL Output: 	DX8GSR0[6]:    WLERR has 		** No Error **
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ***************** DDR3A Leveling Values *********************
arm_A15_0: GEL Output: DDR Clock Period as measured by Leveling Registers:

arm_A15_0: GEL Output:  DX0GSR0:		0x00399D20 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	10 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	57 
arm_A15_0: GEL Output:  DX1GSR0:		0x00399CA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	9 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	57 
arm_A15_0: GEL Output:  DX2GSR0:		0x003B9DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	59 
arm_A15_0: GEL Output:  DX3GSR0:		0x003B9DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	59 
arm_A15_0: GEL Output:  DX4GSR0:		0x003B9DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	59 
arm_A15_0: GEL Output:  DX5GSR0:		0x003B9DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	59 
arm_A15_0: GEL Output:  DX6GSR0:		0x003C9DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	60 
arm_A15_0: GEL Output:  DX7GSR0:		0x00399DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	57 
arm_A15_0: GEL Output:  DX8GSR0(ECC):	0x003B9DA0 
arm_A15_0: GEL Output:  		[14:7] (Write Leveling Period): 	11 
arm_A15_0: GEL Output:  		[23:16] (Read DQS Gating Period): 	59 

arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Delay Values from Write Leveling Registers:

arm_A15_0: GEL Output:  DX0GTR:			0x00005002 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX0LCDLR0:		0x0000001D 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		29 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX1GTR:			0x00005002 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX1LCDLR0:		0x0000001F 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		31 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX2GTR:			0x00005002 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX2LCDLR0:		0x0000002D 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		45 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX3GTR:			0x00005002 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX3LCDLR0:		0x0000002F 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		47 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX4GTR:			0x00005003 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX4LCDLR0:		0x0000003A 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		58 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX5GTR:			0x00005002 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX5LCDLR0:		0x0000004C 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		76 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX6GTR:			0x00005003 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX6LCDLR0:		0x0000004E 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		78 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX7GTR:			0x00005003 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX7LCDLR0:		0x00000053 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		83 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output:  DX8GTR:			0x00005002 
arm_A15_0: GEL Output:  		[13:12] (Rank 0 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  		[15:14] (Rank 1 WL Cycle Latency): 	1 
arm_A15_0: GEL Output:  DX8LCDLR0:		0x00000035 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 WL Delay): 		53 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 WL Delay): 		0 
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Equivalent 90 degree phase shift in delay units, derived from measured period:

arm_A15_0: GEL Output:  DX0LCDLR1:		0x001F1E21 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		33 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay):		30 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		31 
arm_A15_0: GEL Output:  DX1LCDLR1:		0x001D1C20 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		32 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		28 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		29 
arm_A15_0: GEL Output:  DX2LCDLR1:		0x001D1D20 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		32 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		29 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		29 
arm_A15_0: GEL Output:  DX3LCDLR1:		0x001D1D20 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		32 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		29 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		29 
arm_A15_0: GEL Output:  DX4LCDLR1:		0x001D1D20 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		32 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		29 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		29 
arm_A15_0: GEL Output:  DX5LCDLR1:		0x001B1A22 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		34 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		26 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		27 
arm_A15_0: GEL Output:  DX6LCDLR1:		0x001D1C21 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		33 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		28 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		29 
arm_A15_0: GEL Output:  DX7LCDLR1:		0x001A1922 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		34 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		25 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		26 
arm_A15_0: GEL Output:  DX8LCDLR1:		0x001B1B21 
arm_A15_0: GEL Output:  		[7:0] (Write Delay Shift): 		33 
arm_A15_0: GEL Output:  		[15:8] (Read DQS Delay): 		27 
arm_A15_0: GEL Output:  		[23:16] (Read DQSN Delay): 		27 
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Delay Values from Read DQS Gating Leveling Registers:

arm_A15_0: GEL Output:  DX0GTR:			0x00005002 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	2 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX0LCDLR2:		0x00000041 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		65 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX1GTR:			0x00005002 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	2 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX1LCDLR2:		0x00000047 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		71 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX2GTR:			0x00005002 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	2 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX2LCDLR2:		0x0000004C 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		76 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX3GTR:			0x00005002 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	2 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX3LCDLR2:		0x00000055 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		85 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX4GTR:			0x00005003 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	3 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX4LCDLR2:		0x00000008 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		8 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX5GTR:			0x00005002 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	2 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX5LCDLR2:		0x00000069 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		105 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX6GTR:			0x00005003 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	3 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX6LCDLR2:		0x00000055 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		85 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX7GTR:			0x00005003 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	3 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX7LCDLR2:		0x00000012 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		18 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output:  DX8GTR:			0x00005002 
arm_A15_0: GEL Output:  		[2:0] (Rank 0 DQS Gating Latency): 	2 
arm_A15_0: GEL Output:  		[5:3] (Rank 1 DQS Gating Latency): 	0 
arm_A15_0: GEL Output:  DX8LCDLR2:		0x00000064 
arm_A15_0: GEL Output:  		[7:0] (Rank 0 RL Delay): 		100 
arm_A15_0: GEL Output:  		[15:8] (Rank 1 RL Delay): 		0 
arm_A15_0: GEL Output: ****************************************************************************************************************

Hi,

The board based on the above mentionned SoC has DDR3 on DDR3A interface. The DDR3 chip reference is AS4C512M16D3L-12BIN.

We try to configure this DDR3 at 1600 speed with DDR3 clock at 800Mhz.

This currently does not work correctly.

Here are attached the excel datasheet and GEL file log.

Any comment is welcome.

Best Regards.

over 6 years ago

0 Rex Chang over 6 years ago

TI__Guru 50170 points

Hi,

Please go through the following documentation if you haven't, and see if they help.

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#custom-board-addition

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/FAQ.html#useful-ddr-configuration-resources

http://www.ti.com/lit/an/sprabx7/sprabx7.pdf

Rex

0 dr over 6 years ago

Intellectual 280 points

We made some leveling registers measurement on custom board and K2HK EVM board:

EVM

DX:   GTR   LCDLR0   LCDLR1   LCDLR2
0   0x5003   0x45   0x202020   0x24
1   0x5003   0x44   0x1c1b22   0x26
2   0x5003   0x4e   0x1e1e22   0x35
3   0x5003   0x52   0x1f1f21   0x32
4   0x5003   0x61   0x1e1f21   0x5d
5   0x5003   0x6d   0x1e1e1f   0x55
6   0x6003   0x3   0x1f1e21   0x63
7   0x6003   0x7   0x21201f   0x62
8   0x5003   0x51   0x202022   0x4f

Custom board

DX:   GTR   LCDLR0   LCDLR1   LCDLR2
0   0x5002   0x1e   0x1f1e20   0x42
1   0x5002   0x1e   0x1d1c21   0x48
2   0x5002   0x2d   0x1d1c20   0x4b
3   0x5002   0x30   0x1c1c20   0x55
4   0x5003   0x39   0x1d1d20   0xa
5   0x5002   0x4d   0x1b1a21   0x6a
6   0x5003   0x4d   0x1c1b21   0x56
7   0x5003   0x52   0x191821   0x11
8   0x5002   0x33   0x1b1b1f   0x63

How can we explain that some lanes have so low values compared to the other ?

0 Tom Johnson 16214 over 6 years ago in reply to dr

TI__Mastermind 46460 points

dr,

There are multiple delay lines associated with each byte lane. There are both coarse and fine resolution delays lines as well. Depending how the coarse delay line initializes, the fine resolution delay line may have very different values. Also note that leveling operates over multiple clock periods. When the clock boundary is crossed, the delay line values restart back at 0.

Do you see similar results across all of the boards? The pattern should be similar as the routing delays will be very similar across the boards. However, there will be some variation across devices as the delay line increment size varies due to transistor process strength variation. Also, the input and output buffers in the SOC and SDRAM also vary with process variation (and voltage and temperature) so this will also cause the leveling results to differ.

Tom

0 dr over 6 years ago in reply to Tom Johnson 16214

Intellectual 280 points

Hi,

From ddr3 user guide chapter 3.2.2 Programming the SDRAM Refresh Control Register (SDRFC):

According to the DDR3 JEDEC standard, on reset de-assertion the DDRCKE pin must remain low for at

least 500μs before becoming active during power-up initialization. This is achieved by programming a 500

μs refresh period in the SDRFC prior to initialization.

We don't see such programming in u-boot or GEL file.

So what is the status of this comment ?

Thanks.

0 Tom Johnson 16214 over 6 years ago in reply to dr

TI__Mastermind 46460 points

dr,

I beleive you are referring to Keystone Architecture DDR3 Memory Controller User's Guide (SPRUGV8E). This document is associated with KeyStone I devices. You are using the 66AK2H14 which is from our KeyStone II family which has a completely different DDR PHY and Controller. I am sure that you will find may things stated in SPRUGV8E that are not implemented in the GEL and Linux code for the 66AK2H14.

You should be referencing the Keystone II Architecture DDR3 Memory Controller User's Guide (SPRUHN7C). All documents relevant for commissioning DDR on 66AK2H14 are linked from the KeyStone II DDR3 Interface Bring-Up Application Report (SPRACM0) at the link below.

Tom

0 dr over 6 years ago in reply to Tom Johnson 16214

Intellectual 280 points

Hi,

I am refering to the Keystone II document.

0 Tom Johnson 16214 over 6 years ago in reply to dr

TI__Mastermind 46460 points

DR,

You are correct that section 3.2 of document SPRUHN7C for KS-II contains that incorrect text. If you compare it with SPRUGV8E, which is the equivalent document for KS-I, you can see that it was copied forward from the prior document. This text is not correct. I will file a request to get this updated. The DDR3 PHY in the KeyStone-II devices is fully autonomous and does not need any of the detailed management required in the older version.

The Keystone II DDR3 Initialization Application Report SPRABX7 contains a description of the PHY initialization sequence and then details the software steps needed to complete this sequence. Figure 1 shows these steps. Example 7 provides the steps needed to perform the actual PHY initialization steps which triggers the portion of the initialization where CKE is held low for the minimum 100us.

Tom

Processors

Processors forum

66AK2H14: DDR3 configuration problem