AM3351: DDR2 signal integrity

Hi Francois, since we comply with JEDEC standards, you can find all of the input specs for the controller in the DDR3 JEDEC specification JESD79-3F.  You will find that Vix for DQS is -150 to 150mV.  Since you have different scales on the scope for the signals, it is tough for me to tell by that picture if you are within that spec.

Regards,

James

Hi James,

Thank you for the information!

When I look at our implementation we are running in DDR2 modes, which specifies an output Vox. The DDR3 Jedec does not specify a Vox but I see in datasheets of DDR3 manufacturers it is specified also as Vref +/- 150mV. So that would mean there is not margin between output of the DDR3 and input of the Sitara physical. In my understanding the Jedec is written from the DDRx device point of view, so it is correct that the Vix of the Sitara DDR phy requires Vref +/- 150mV? Without having any margin on this parameter?

Sorry for the unclear scope plot, what we see it that the Vix at the Sitara DDR phy is influenced by some what I believe is crosstalk. Which is visible when the green signal (DQ) is changing logic state. Here the crossing point is lower or higher compared to when DQ is keeping its logic level. When I make a histogram of the Vix I get the following measurement results:

So from the histogram it is clear the Vix (at the Sitara) is changing up/down due to 'external' influence I believe. So that's why I ask about the input spec of the Sitara DDR phy, would this behavior be an issue? (Additionally like mentioned before we experience no problems or instability).

Regards,

François

Hi Francois,

i believe table 27 of the spec shows the single ended margins for DQS. Also note the VSEL and VSEH components of the Vix in table 28.  The effect of DQ switching is concerning.  This is where the design guidelines from the datasheet would help to mitigate these issues.  Do you have any violations of these guidelines, especially signal to signal spacing?

Regards,

James

Sorry Francois, i originally pointed you to the DDR3 JEDEC standard.  The DDR2 standard is JESD79-2F.  Table 23 in the DDR2 spec shows a tolerace of 175mV for the crossing point of Vix, whereas the Vox spec is 125mV.  Ideally your histogram should be gaussian with a peak at 0.75V.  It looks like your peak is around 0.8V and the outliers are beyond spec.  Check you voltage levels on VDDQ and VREF, although i think ultimately the issue might be in your routing and crosstalk which you indicated.

Regards,

James

Hi James,

An okay thanks for the clarification and no problem of course.

About our design I have checked spacing between DDR signals and I see violations when checking according the datasheet. Because we have a dense design, we were not able to get more spacing between signals. So, it is highly likely this is the root cause. For the write we don't have any problems with this because the Sitara can reduce the drive enough but the DDR2 device does not support this feature.

When I was analyzing the effect on the DQS_p/n crossing point of a read at the Sitara I see the following parameters which are possibly influenced due to change in duty cycle due to the crossing point violation:

tDQSCK = +/- 450 ps

tDQSQ (max) = 300 ps
tQH = tHP - tQHS where tHP = min(tCL, tCH) and tQHS = 300 ps

(Parameters are output parameters from the DDR2 device)

When I measure these influenced parameters, the outcome is pass (within Jedec spec). Additionally, we have tested our platform with memory testing (also at high temperature to stress even more) but we observe a good and stable operation.

Can you elaborate on this? Do you share my analysis or do I overlook parameters which are also influenced on the violation of the crossing point of the DQS_p/n

Regards,

François

Hi Francois,

the crossing point violation will really just eat away at your setup/hold timing margins.  With your tight board and somewhat slow clock rates, you probably have a lot of margin to work with, so the varying crossing point is not affecting you.  The read data will be captured by the controller well away from the DQS crossing point.  I think your analysis is sound and sounds like you have done proper stress testing.

Regards,

James