AM6546: Package skew

Hello Biser,

My self Akash P from analysis team.

I was going through the simulation for DDR4 interface considering AM6546 as driver.

While simulating the DDR4 lines I was observing that some of the signals are quite good with better margins, where as some of the signals are bad and not meeting the required specifications.

If I use any other driver instead of AM6546 device I am getting good results for the failing signals.

Is this because of the drive strength of AM6546 device?

Please reply and do the needful

Warm Regards,

Akash P

Hi Akash,

Can you elaborate / provide details on the following statement?

While simulating the DDR4 lines I was observing that some of the signals are quite good with better margins, where as some of the signals are bad and not meeting the required specifications.

As an example, a few details that would be helpful:

• what specification is being violated
• are you performing write or read simulations
• which signals are passing vs. failing
• simulation environment (models being used, etc.)

Also, have you confirmed your board design follows the AM65x layout / routing guidelines?

Thanks,
Kevin

Akash,  (I accidentally clicked the "TI thinks resolved" you can reject that for now ...)

Are you following the DDR layout guidelines appnote:

AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A)

Especially for your question, refer to this table: 

 Table 9. CK and ADDR_CTRL Routing Specifications

I assume longest and shortest length nets is referring to the PCB trace lengths?  What is the longest and shortest for your PCB?

Thanks,

Kyle

Kyle,

Yes, we have followed the routing specification from the app note.

And the longest trace in our PCB is of 4.648 in and shortest traces of 4.495 in.

Also, we are performing analysis at 3200 MT/s.

Warm Regards,

Akash P

Akash,

AM6546 does not support DDR4-3200. The fastest data rate supported is DDR4-1600.

Also, the address pins should be skew matched - see Table 9 in the document referenced by Kyle.

Best regards,
Kevin

Hello Kevin,

Agreed your point, as I mentioned it is 3200 MT/s (Mega Transfers per second) which is nothing but 1600 MHz (Mega Hertz)

Also, we have matched within the acceptable tolerance suggested in data sheet.

Warm Regards,

Akash P

Hi Akash,

To clarify my previous statement, the maximum DDR clock speed is 800 MHz (such that the data is transferring at 1600 MHz, 1600 MT/s).  A 3200 MHz data rate is not supported.

Best regards,
Kevin

Dear Kevin,

Sorry for the inconvenience, I had simulated Address lines at the frequency of 800 MHz since it is supporting SDR frequency which is as per the datasheet.

But still i am not getting proper eye diagram for A13 net.

Please suggest what needs to be done on this issue.

Regards,

Akash P

Hi,

Can you please look into this issue on priority and suggest a solution.

We are stuck at Simulation and are unable to proceed to release the Gerber for Manufacturing.

Regards

Tauseef Kazi

Hi Kevin,

Can you please look into this issue on priority and suggest a solution.

We are stuck at Simulation and are unable to proceed to release the Gerber for Manufacturing.

Regards

Tauseef Kazi

Akash,

When you say you're simulating address at 800 MHz, do you mean the eye is nominally 1.25 ns wide?  Address should switch at 1/2 the frequency of the clock - i.e., low to high or high to low only relative to the rising edge of the clock.

Can you show a picture of a passing scenario and a failing scenario?  

Regards,

Kyle

Kyle,

We have did the simulation at 800 MHz as our DDR device supports SDR frequency. 

Also, attaching the waveform for passing and failing nets as requested, let me know if you have problem in downloading attached file.

Please check and do the needful.

Warm regards,

Akash pDDR4.zip

Hi Kyle,

Is there any update on this.

Regards

Tauseef Kazi

Tauseef,

Can you resimulate using the model : DWC_D5MP4_34.

Also, are you following the layout guidelines appnote, especially section 2.15.2 CK and ADDR_CTRL Routing Limits

AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A)

If one signal route looks good and one route looks bad, other than the length difference you should make sure there are no other anomalies (too many vias, stubs?) on the 2nd route.

Thanks,

Kyle

Hi Kyle,

We have followed the layout guidelines app note, especially section 2.15.2 CK and ADDR_CTRL Routing Limits strictly.

We will resimulate with the suggested model and share the results.

Regards

Tauseef Kazi