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TDA4VM: TDA4VM SerDes Clock Termination

Nick Fan1
Prodigy 60 points
Part Number: TDA4VM


Hi Expert,

I find that TDA4VM could provide internal PLL clock (100MHz) needed for PCIe operation. So we might remove the external clock generator for PCIe.  (https://e2e.ti.com/support/processors/f/791/t/865372)

I have checked with our local TI FAE, TDA4VM also could internal PLL clock(100MHz) for DP operation before.

The question what I want to ask is :

If I select to use internal PLL clock as SerDes reference clock input, then the pin of TDA4VM reference clock is not used. How to correctly handle them? Do we need to push them down with 50Ohm resistor?  I find that in TDA4VM EVM, some SerDes clock input pins (SerDes0/ SerDes1/ SerDes2 ) has reserved the termination resistor packages, some module (SerDes3/ SerDes4) does not reserved.

  • 0
    TI__Mastermind 22820 points

    Hi Nick,

    No need for any special handling for Serdes I/Os. Pads for resistors to GND are nice to have for any debugging in the future.

    Please note that if you have PCIe ports in the design and you wish to skip the external clock generator, then the internal (SoC) 100-Mhz clock needs to be routed to the external PCIe devices/slots. I.e. PCIE_REFCLK0/1/2/3 must become outputs (SW configurable) and connected to external PCIe device. More details about PCIE reference clock distribution can be found in the PCIe specs.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Prodigy 60 points

    Hi Expert,

    Thanks for your reply firstly. I have some puzzle about your reply.

    If I use TDA4VM connect some other device with PCIe, such as another SoC_B. In general, TDA4VM need PCIe reference clock input., and SoC_B also need another PCIe reference clock input.

    Now, TDA4VM could use the internal PLL clock as its reference clock input to replace the external clock generator. Of course, SoC_B could use TDA4VM PCIe reference clock output. In my original understanding, SoC_B also could use the external clock generator as reference clock input.

    On your reply, it seems that we must use the TDA4VM clock output for SoC_B, there is no external clock generator input option, am I right?  However, I roughly remember that SerDes does not need external synchronous clock input. 

  • 0 in reply to Nick Fan1
    TI__Mastermind 22820 points

    Nick,

    PCIe needs common! 100-MHz PLL reference clock for the participants in the PCIe link. The clock  source can be either an external clock oscillator IC (TI boards), either PCIe root complex, i.e. TDA4. More details can be found in PCIe standard.