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Original question:

DRA756: No output clock for PHY-less connection

DRA756: Cannot change output clock for PHY-less connection

user6232558
Intellectual 435 points
Part Number: DRA756
Other Parts Discussed in Thread: TDA2

Hi all,

There is a customed board with DRA756 chip, each peripheral works fine except for ethernet. After fixing no output clock problem (e2e.ti.com/.../3289760 with help from Santhana, clock of TXC is always 2.5MHz when booting to u-boot or booting to Linux. Below is some details about u-boot and Linux configuration.

Booting log of the whole process is here

3808.boot_log_20200424.log
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U-Boot 2018.01-00566-g0f1ad58-dirty (Apr 24 2020 - 15:39:42 +0800)
CPU : DRA756-GP ES2.0
Model: TI DRA756
Board: DRA756 REDRAM: 2 GiB
NAND: 0 MiB
MMC: OMAP SD/MMC: 0
MMC Device 1 not found
*** Warning - No MMC card found, using default environment
In: serial@4806a000
Out: serial@4806a000
Err: serial@4806a000
invalid mmc device
Net: Could not get PHY for ethernet@48484000: addr -17123512
Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot: 4 3 2 1 0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
232 bytes read in 1 ms (226.6 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
4014592 bytes read in 177 ms (21.6 MiB/s)
99222 bytes read in 6 ms (15.8 MiB/s)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffe4000, end 8ffff395 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.14.79-g3438de3474 (oe-user@oe-host) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #1 SMP PREEMPT Thu Jan 31 10:19:19 UTC 2019
[ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] OF: fdt: Machine model: LM DRA756
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[ 0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[ 0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[ 0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[ 0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[ 0.000000] cma: Reserved 128 MiB at 0x00000000b0000000
[ 0.000000] OMAP4: Map 0x00000000fed00000 to fe600000 for dram barrier
[ 0.000000] DRA752 ES2.0
[ 0.000000] percpu: Embedded 15 pages/cpu @eed58000 s31372 r8192 d21876 u61440
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 517696
[ 0.000000] Kernel command line: console=ttyO0,115200n8 elevator=noop root=/dev/mmcblk0p2 rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=128M@0xB0000000 rootfstype=ext4 snd.slots_reserved=1,1
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 1747808K/2077696K available (8192K kernel code, 346K rwdata, 2636K rodata, 2048K init, 282K bss, 34976K reserved, 294912K cma-reserved, 1160192K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  and ethtool related probing log is here
ethtool_20200424.log
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root@dra7xx-evm:~# ethtool -S eth0
NIC statistics:
Good Rx Frames: 0
Broadcast Rx Frames: 0
Multicast Rx Frames: 0
Pause Rx Frames: 0
Rx CRC Errors: 0
Rx Align/Code Errors: 0
Oversize Rx Frames: 0
Rx Jabbers: 0
Undersize (Short) Rx Frames: 0
Rx Fragments: 0
Rx Octets: 0
Good Tx Frames: 64
Broadcast Tx Frames: 27
Multicast Tx Frames: 37
Pause Tx Frames: 0
Deferred Tx Frames: 0
Collisions: 0
Single Collision Tx Frames: 0
Multiple Collision Tx Frames: 0
Excessive Collisions: 0
Late Collisions: 0
Tx Underrun: 0
Carrier Sense Errors: 0
Tx Octets: 12656
Rx + Tx 64 Octet Frames: 0
Rx + Tx 65-127 Octet Frames: 37
Rx + Tx 128-255 Octet Frames: 0
Rx + Tx 256-511 Octet Frames: 27
Rx + Tx 512-1023 Octet Frames: 0
Rx + Tx 1024-Up Octet Frames: 0
Net Octets: 12656
Rx Start of Frame Overruns: 0
Rx Middle of Frame Overruns: 0
Rx DMA Overruns: 0
Rx DMA chan 0: head_enqueue: 1
Rx DMA chan 0: tail_enqueue: 127
Rx DMA chan 0: pad_enqueue: 0
Rx DMA chan 0: misqueued: 0
Rx DMA chan 0: desc_alloc_fail: 0
Rx DMA chan 0: pad_alloc_fail: 0
Rx DMA chan 0: runt_receive_buf: 0
Rx DMA chan 0: runt_transmit_bu: 0
Rx DMA chan 0: empty_dequeue: 0
Rx DMA chan 0: busy_dequeue: 0
Rx DMA chan 0: good_dequeue: 0
Rx DMA chan 0: requeue: 0
Rx DMA chan 0: teardown_dequeue: 0
Tx DMA chan 0: head_enqueue: 64
Tx DMA chan 0: tail_enqueue: 0
Tx DMA chan 0: pad_enqueue: 0
Tx DMA chan 0: misqueued: 0
Tx DMA chan 0: desc_alloc_fail: 0
Tx DMA chan 0: pad_alloc_fail: 0
Tx DMA chan 0: runt_receive_buf: 0
Tx DMA chan 0: runt_transmit_bu: 0
Tx DMA chan 0: empty_dequeue: 64
Tx DMA chan 0: busy_dequeue: 0
Tx DMA chan 0: good_dequeue: 64
Tx DMA chan 0: requeue: 0
Tx DMA chan 0: teardown_dequeue: 0
root@dra7xx-evm:~# ethtool eth0
Settings for eth0:
Supported ports: [ TP AUI BNC MII FIBRE ]
Supported link modes: 1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
. And key registers value about mac is here
mac_reg_value_20200424.log
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root@dra7xx-evm:/mnt# ./memread.sh
try to get 0x4A003650
10000
try to get 0x4A003654
10000
try to get 0x4A003658
10000
try to get 0x4A00365C
10000
try to get 0x4A003660
10000
try to get 0x4A003664
10000
try to get 0x4A003668
50000
try to get 0x4A00366C
50000
try to get 0x4A003670
50000
try to get 0x4A003674
50000
try to get 0x4A003678
50000
try to get 0x4A00367C
50000
root@dra7xx-evm:/mnt# omapconf read 0x48485288
00000000
omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!
root@dra7xx-evm:/mnt# omapconf read 0x48484D84
000000A1
omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!
root@dra7xx-evm:/mnt#
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
.

For u-boot, mac related configuration is here. mux_data.h is update with new pad configuration and pad IO delay. However, pad IO delay is genrated by TI pin mux tool and not changed.

For Linux configuration, mac related dts is shown below

Trails below are already been done but clock is still 2.5MHz.

  1. change linux dts, phy-mode = "rgmii-id", probing at linux terminal;
  2. change linux dts, change fixed-link.speed to 10, 100, 1000, , probing at linux terminal
  3. change uboot dts, add fixed-link and remove PHY properties and phy-mode = "rgmii-rxid" , probing at uboot terminal

Hope someone share me some insights. Thanks very much.

Best Regards,

Daniel

  • 0
    TI__Mastermind 33010 points

    Hi Daniel,

    According to the TRM, the TXC is set to 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.



    Can you check what is the value of SL_MACCONTROL[15] IFCTL_A bit?

    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your answering this post and support.

    I have noticed your posted figure. But I am curious about the reason why TXC clock is always 2.5MHz, even though 10, 100, 1000MHz fix bit rate have been tried.

    The value of SL_MACCONTROL[15] IFCTL_A bti is 0, and its register value is 0x00A1. You can find more information by checking mac_reg_value_20200424.log file I posted in the topic.

    Besides, I am also curious about which registers decide TXC clock frequence. Then I dump clock tree of the customed board with omapconf ctt dump. And printed result is here 

    cct_custom_20200426.log
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    DeviceName DRA75X_SR2.0
    0x4A005100 0x00000110
    0x4A005120 0x00000007
    0x4A00512C 0x00010A04
    0x4A005130 0x00000002
    0x4A00513C 0x00000204
    0x4A005140 0x0000023E
    0x4A005144 0x00000005
    0x4A005154 0x00000005
    0x4A005158 0x00000204
    0x4A00515C 0x00000006
    0x4A005160 0x00000007
    0x4A00516C 0x00803200
    0x4A005170 0x00000201
    0x4A00519C 0x00000000
    0x4A0051A0 0x00000007
    0x4A0051AC 0x00010A04
    0x4A0051B0 0x00000002
    0x4A0051DC 0x00000000
    0x4A0051E0 0x00000005
    0x4A0051EC 0x00800000
    0x4A0051F0 0x00000001
    0x4A0051F4 0x00000001
    0x4A005210 0x00000007
    0x4A00521C 0x00010A04
    0x4A005220 0x00000202
    0x4A005228 0x00000208
    0x4A005234 0x00000007
    0x4A005240 0x00004B01
    0x4A005244 0x00000001
    0x4A005248 0x00000003
    0x4A005254 0x00000000
    0x4A005284 0x00000005
    0x4A005290 0x00000000
    0x4A005294 0x00000001
    0x4A0052A4 0x00000000
    0x4A0052A8 0x00000007
    0x4A0052B4 0x0000FA04
    0x4A0052B8 0x00000204
    0x4A0052C0 0x00000228
    0x4A0052C4 0x00000208
    0x4A0052D8 0x00000007
    0x4A0052E4 0x00010A04
    0x4A0052E8 0x00000202
    0x4A005420 0x00070000
    0x4A005520 0x01070000
    0x4A005550 0x00030000
    0x4A005558 0x00030000
    0x4A005560 0x00030000
    0x4A005568 0x00030000
    0x4A005570 0x00030000
    0x4A005578 0x00030000
    0x4A005580 0x00030000
    0x4A005620 0x00070000
    0x4A005660 0x00070000
    0x4A0056A0 0x00070000
    0x4A005744 0x00020002
    0x4A005764 0x00000001
    0x4A008140 0x00000007
    0x4A00814C 0x00006004
    0x4A008150 0x00000804
    0x4A008158 0x00000003
    0x4A00815C 0x00000004
    0x4A008160 0x0000000A
    0x4A008164 0x00000002
    0x4A008180 0x00000007
    0x4A00818C 0x0401E009
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    and hope this would help solving the problem.

    Thanks for your help and hope for your reply. Thanks a lot!

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    Sorry, I did not check those files.
    According to the register value, the interface is in 10 Mbps operation. What was the speed value in dts when this register value was dumped?





    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    TI__Mastermind 33010 points

    Hi Daniel,

    Noticed that GIG bit (bit 7) is set, indicating gigabit mode. Ignore the previous comment.

    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    TI__Mastermind 33010 points

    Can we do some basic tests on u-boot level?

    Could you get the value of SL_MACCONTROL register for various speed-mode settings in u-boot dts?
    (You can read the register value at u-boot console using md command)

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your reply.

    Under different speed sed in uboot dts file, results of SL_MACCONTROL are read as 0x00000000. Details are shown below :

    Hope for your reply and thanks for your support again.

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    Is Ethernet functional from u-boot?

    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your quick reply.

    I cannot sure about this and Ethernet maybe not work during uboot. There maybe some missing during porting. Code created in board/ti/ and arch/arm/dts are zip here5873.dra7xx_customed.zip.

    Could you please help checking these files ? Thanks very much !

    And I notice that for mac node in Linux dts file shown below, there is pinctrl node. For uboot dts file, how to offer pinctrl information ? I also notice evm uboot dts file dra7-evm.dts does not include pinctrl for mac node. Shold I need to change uboot code or dts file based on the uploaded zip file?

    Best Regards,,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    In case of u-boot the pinmux happens in board/ti/dra7xx/evm.c and board/ti/dra7xx/mux_data.h

    Is Ethernet functional on Linux Kernel?
    Can you do those experiments I asked for on Kernel instead of u-boot?



    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your reply and support.

    I suppose Ethernet functional on Linux kernel. Mentioned in the topic, no clock output problem has been fixed with adding pinctrl node in Linux dts file. But I am nore whether Ethernet functional rightly on Linux kernel.

    Hope for your reply and thanks a lot.

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    Ideally pinmux should happen in u-boot. Both pinmux settings and IODELAY settings are done in u-boot.
    For current debug it's OK to continue with pinmux in kernel.

    Could you get the SL_MACCONTROL register details from kernel for different speed modes (10, 100, 1000)?


    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your reply and explanation.

    Different speed in dts file is set and compiled with make dtbs command. For speed (10, 100, 1000), SL_MACCONTROL value is (0x00040021, 0x00008021, 0x000000A1). Details is shown below.

    --- Speed is 10Mbps---

    ---Speed is 100Mbps---

    ---Speed is 1000Mbps---

    Thanks for your support and hope for your reply.

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    SL_MACCONTROL registers look OK for speed modes selected in dts.

    Could you also check the register WR_RGMII_CTL (0x48485288) for different speed modes?


    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your quick response and support.

    Register values WR_RGMII_CTL under different speed (10, 100, 1000) are both 0x00000000. Results are listed below.

    ---Speed is 10Mbps---

    ---Speed is 100Mbps---

    ---Speed is 1000Mbps---

    Thanks for your help and hope for your reply.

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    Could you also check the CTRL_CORE_CONTROL_IO_1 (0x4A002554) register values?

    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    TI__Mastermind 33010 points

    Hi Daniel,

    Could you test with below changes in Kernel and check the behavior?
    Please also check WR_RGMII_CTL register again after this change.

    diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 6bfd2db25924..64cc7e0d7d6d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1168,6 +1168,8 @@ static void _cpsw_adjust_link(struct cpsw_slave *slave,
                else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
                        mac_control |= BIT(18); /* In Band mode */

+               mac_control |= BIT(18);
+
                if (priv->rx_pause)
                        mac_control |= BIT(3);

    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your support and help. Sorry for this lately reply due to International Workers' Day in these days.

    Before applying your advice for changing kernel code, for CTRL_CONTROL_IO_1(0x4A002554) under varied speed, its value is always 0x0003302. Detailed results are here:

    ---speed is 10Mbps---

    ---speed is 100Mbps---

    ---speed is 1000Mbps---

    After changing kernel, code is shown below. However, there maybe two problems. At first, WR_RGMII_CTL(0x48485288) is still not change, which is 0x00000000. For second, I doubt whether newly added is executed or not. Because added cpsw_info print content is not found in boot log

    linux_bootlog_afterkernelchange_20200506.log
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    reboot
    Stopping NFS status monitor for NFSv2/3 locking....
    [ OK Stopping Session c1 of user root.
    [ OK ] Stopped Daily Cleanup of Temporary Directories.
    [ OK ] Stopped target Multi-User System.
    Stopping Job spooling tools...
    Stopping Hardware RNG Entropy Gatherer Daemon...
    Stopping strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf...
    [ OK ] Stopped target Login Prompts.
    Stopping Serial Getty on ttyS0...
    Stopping Getty on tty1...
    [ OK ] Stopped target Containers.
    Stopping Periodic Command Scheduler...
    Stopping System Logging Service...
    Stopping thermal-zone-init.service...
    Stopping Lightning Fast Webserver With Light System Requirements...
    Stopping Kernel Logging Service...
    Stopping D-Bus System Message Bus...
    Stopping User Manager for UID 0...
    [ OK ] Stopped Kernel Logging Service.
    [ OK ] Stopped Hardware RNG Entropy Gatherer Daemon.
    [ OK ] Stopped D-Bus System Message Bus.
    [ OK ] Stopped strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf.
    [ OK ] Stopped Job spooling tools.
    [ OK ] Stopped System Logging Service.
    [ OK ] Stopped TI IPC Daemon.
    [ OK ] Stopped Periodic Command Scheduler.
    [ OK ] Stopped Lightning Fast Webserver With Light System Requirements.
    [ OK ] Stopped NFS status monitor for NFSv2/3 locking..
    [ OK ] Stopped Serial Getty on ttyS0.
    [ OK ] Stopped Getty on tty1.
    [ OK ] Stopped User Manager for UID 0.
    [ OK ] Stopped thermal-zone-init.service.
    [ OK ] Stopped Session c1 of user root.
    Stopping matrix-gui-2.0.service...
    [ OK ] Removed slice User Slice of root.
    Stopping Login Service...
    [ OK ] Removed slice system-getty.slice.
    Stopping Permit User Sessions...
    [ OK ] Removed slice system-serial\x2dgetty.slice.
    [ OK ] Stopped target Host and Network Name Lookups.
    Stopping Network Name Resolution...
    Stopping RPC Bind Service...
    [ OK ] Stopped Login Service.
    [ OK ] Stopped RPC Bind Service.
    [ OK ] Stopped Network Name Resolution.
    [ OK ] Stopped matrix-gui-2.0.service.
    [ OK ] Stopped Permit User Sessions.
    Stopping gdbserverproxy.service...
    [ OK ] Stopped target Network.
    Stopping Network Service...
    [ OK ] Stopped gdbserverproxy.service.
    Stopping rng-tools.service...
    [ OK ] Stopped rng-tools.service.
    Stopping thttpd.service...
    [ OK ] Stopped Network Service.
    [ OK ] Stopped thttpd.service.
    Stopping telnetd.service...
    [ OK ] Stopped telnetd.service.
    Stopping weston.service...
    [ OK ] Stopped weston.service.
    [ OK ] Stopped target Remote File Systems.
    Stopping rc.pvr.service...
    [ OK ] Stopped rc.pvr.service.
    Stopping uim-sysfs.service...
    [ OK ] Stopped uim-sysfs.service.
    [ OK ] Stopped target Basic System.
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    or dmsg.

    The approach I update linux kernel is here, which was verified with adding serial usb device module support. Therefore, I am sure kernel file is compile and updated.

    * modify makefile under tisdk path to avoid linux/.config file coverred

    * make linux and make linux_install

    * delete original linux kernel and lib/module filies, then copy with newly generated ones from install path

    Hope for your reply and thank very much!

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    Your procedure to update is correct.
    Could you try changing cpsw_info() to pr_err() and check the prints?

    The CTRL_CONTROL_IO_1 and SL_MACCONTROL register look ok.

    We need to move the pinmux to u-boot and also add iodelay values in u-boot and check the behavior.
    You can look at TI EVM example in u-boot (board_ti/dra7xx/evm.c, mux_data.h)

    Regards,
    Vishal




  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your reply and guidance.

    For WR_RGMII_CTL, why the valus of this register under different are both 0x00000000 ? Is there any problem reflected by this ?

    For iodelay, the files I uploaded before and attached here (7752.dra7xx_customed.zip) again. As you can see, in zip file, mux_data.h and customed.c files contains iodelay related code, which are shown in below figures. The delays values are generated with TI pinmux tool, is there any need to compensate the values and how to do the compensation work ?

    For checking print in boot log, after changing cpsw_info to pr_err, it works and result is shown below.

    Thanks for your support and hope for your reply !

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    Expert 1665 points

    Does networking work for you in u-boot?

    setenv ipaddr 192.168.0.111
    => ping 192.168.0.110
    link up on port 1, speed 100, full duplex
    Using ethernet@046000000 device
    host 192.168.0.110 is alive

  • 0 in reply to Grygorii Strashko50
    Intellectual 435 points

    Hi Grygorii,

    Thanks very much for your advice and help.

    Some background needs to be declare right here. Below figure is posted in another thread mentioned in the topic. TDA2 is connected to Marvell Switch 88E6321(not 88EA6321) port 2. Switch chip is controlled by a MCU running bare-metal code without IP stack. And this local network is not connect to external network. For controlling switch, only port forwarding is achieved between port 5 and port 6. Due to network issue in TDA2 side, port forwarding function is still being verified between port 2 and port 5.

    When using ping command in u-boot, no signal can be found in EMAC_TXD0 by probing P2_RXD0 whether switch is enabled by MCU or not. So I suppose network is not working in u-boot.

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Hi Daniel,

    Can you stop at u-boot and make sure the SL_MACCONTROL and other registers values for different speed mode?
    Is the clock still at 2.5 MHz at u-boot also?

  • 0 in reply to user6232558
    Expert 1665 points

    hi Daniel,

     I've asked about u-boot, because it's usually easier to debug in u-boot, but if you need to load MCU FW or there are init races MCU vs DRA7 then it might be not a good choice.

    Following information you've provided in this thread, there are seems *no issues* in Kernel - all SW does what it should and CPSW side configured properly.

    But WR_RGMII_CTL is 0 and RGMII link not established (RGMII vs RGMII). 

    There is one thing I'd like to ask you to try/verify - pull up/down configuration  of RGMII pins.

    Note. DRA7 SW design assume pins have to be configured by u-boot only - not Linux Kernel. 

  • 0 in reply to Vishal Mahaveer
    Intellectual 435 points

    Hi Vishal,

    Thanks for your reply.

    There is no clock output. Under different emac speed, {0x48484D84, 0x48485288, 0x4A002554} are identical and equal to {0x00000000, 0x00000000, 0x00003302}.

    In before measurement, 2.5MHz clock is caused by the process of booting to Linux kernel and reboot to u-boot phase. So, at this time, I just stop at u-boot without booting to Linux kernel. Besides, swith chip is well configured and port connected to DRA756 chip is also configured.

    Then, I check pinmux registers at uboot for EVMX777G-01-40-00 (evm board) and the customed board. It seems that emac is not configured during uboot.

    figure - pinmux reg of the customed board

    figure - reg value of evm board

    I think problem maybe located at u-boot. And It hope more advices related to u-boot. Thanks very much !

    --- 20200515 progress with whole night locating problem ---

    For evm board, after executing uboot/driver/net/cpsw.c -> cpsw_gmii_sel_dra7xx -> writel(reg, priv->data.gmii_sel), EMAC[0]_TXC is able to output clock. But for out customed board, there is no clock at all when running over the same location.

    Then reg and reg write value are compared, which are both {0x4a002554, 3302}.

    So, could you please share any insights about what leads no clock output ? Thanks again.

    Best Regards,

    Daniel

  • 0 in reply to Grygorii Strashko50
    Intellectual 435 points

    Hi Grygorii,

    Glad to see your reply and thankful for your advice.

    In MCU power on sequence, MCU powers on DRA7 after configuring serial port and switch chip. There should be no races for MCU vs DRA7. However, your reply remind me of the importance about switch clock. In posted content or test result, switch clock is not enable. Then I enable switch input clock and do some tests shown below and found interesting results:

    * switch port 2 connects to DRA7

    Result or confusion I want to share with you.

    * uboot surely has problem of configuring emac, because there is no clock output when directing booting to uboot instead of rebooting to uboot

    * when enable input clock for switch, emac output clock is 25MHz after Starting kernels... and then it change to 2.5MHz after init cpsw. However, when disable switch input clock, emac output clock keep at 2.5MHz after Starting kernels...

    * Should switch to be well configured before powering on DRA7 or before DRA7 configuring CPSW module ?

    Thanks for your insights and hope for your reply again !

    Best Regards,

    Daniel

  • 0 in reply to user6232558
    TI__Mastermind 33010 points

    Clock not being set in u-boot is discussed in new ticket
    https://e2e.ti.com/support/processors/f/791/t/906069

  • 0 in reply to Vishal Mahaveer
    TI__Mastermind 33010 points

    Hi Daniel,

    The u-boot no clock issue was root caused to pin mux not being done in u-boot (calibrate_iodelay API failure)
    This needs to be root caused as the IO lines will have problems without proper iodelay recalibration.

    Regards,
    Vishal