"Implementing DDR2/3 PCB Layout on the TMS320C6A816x..." application report

Michael Iversen

The application report "Implementing DDR2/3 PCB Layout on the TMS320C6A816x Integra DSP+ARM Processor" is mentioned in section 8.17.3 of the TMS320C6A816x datasheet.

Can you please let me know when the report will be released ?

Thanks,

Michael

over 14 years ago

0 MarcPyne over 14 years ago

TI__Mastermind 25055 points

Michael,

Sorry for the confusion. The DDR2 Layout guidelines are already included in the C6A816x datasheet and a revision of the datasheet will be released soon that includes the DDR3 layout guidelines. The DDR2/3 memory device timing can be found in its own datasheet. There are no plans to release a separate application report.

Regards,
Marc

0 Bonzai over 14 years ago

Expert 1025 points

follow this threat

http://e2e.ti.com/support/dsp/integra_dsparm/f/625/t/91652.aspx

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"Implementing DDR2/3 PCB Layout on the TMS320C6A816x..." application report