OSPI maximum clock frequency configuration

Hi,

Can you please ley me know which SDK version is this? Also please point me to the code snippet where you see the division happening.

Regards,

Karan

Hi ,

I am using SDK 1.0 version. The clock is divided in the OSPI_open_v0 function of ospi_V0.c. (Line588)

Thank you.

Hi,Karan

Do you have a solution to this issue? Looking forward to your reply, thank you。

Hi,

I will have an update by tomorrow.

Regards,

Karan

Hi,

yajuan ma said:

How to use data training to derive a maximum frequency of  SDR?

In DAC mode, PHY is enabled by default, the driver does a PHY calibration either in SDR or DDR mode in order to operate in 133 MHz or 166 MHz clock.

yajuan ma said:

TI's demo program main_ospi_flash_test.c sets the OSPI clock to 133MHz in the INDAC mode, but then divides the clock with a baud rate divider, so that I ended up on the clk pin of OSPI FLASH The actual clock frequency measured is the frequency after frequency division. So how should I make the clock frequency on the clk pin of OSPI FLASH be 133MHz?

In INDAC mode, PHY is disabled by default, the driver needs to use a lower clock when PHY is disabled, so we set the clock divider to 32 in the driver.

Regards,

Karan

Hi,

1.In DAC mode, PHY is enabled by default, the driver does a PHY calibration either in SDR or DDR mode in order to operate in 133 MHz or 166 MHz clock.

In this mode, I can read the data in the memory after flash is open, but I cannot erase and write (the flash chip is cypress S28HS512), what is the reason?...

2.In INDAC mode, PHY is disabled by default, the driver needs to use a lower clock when PHY is disabled, so we set the clock divider to 32 in the driver.

Can I enable PHY mode in INDAC mode to reach 133MHZ or 166MHZ?

3.In the datasheet, even if data training is not used, that is, the PHY mode is not turned on, the 1.8V chip clock frequency can reach more than 140 MHZ, but currently I set the clock frequency to 66.66 MHZ to work normally. After setting a larger clock frequency, the flash write operation will fail.May I ask what is the reason?

Hi,

yajuan ma said:

In this mode, I can read the data in the memory after flash is open, but I cannot erase and write (the flash chip is cypress S28HS512), what is the reason?...

In DAC as well as INDAC mode the read/write/erase should be possible. The only mode in which the write and erase won't work is the XIP mode. In case you have XIP mode enabled in DAC mode this is expected.

yajuan ma said:

Can I enable PHY mode in INDAC mode to reach 133MHZ or 166MHZ?

As far as I know PHY training is only for DAC mode, but I can confirm.

yajuan ma said:

.In the datasheet, even if data training is not used, that is, the PHY mode is not turned on, the 1.8V chip clock frequency can reach more than 140 MHZ, but currently I set the clock frequency to 66.66 MHZ to work normally. After setting a larger clock frequency, the flash write operation will fail.May I ask what is the reason?

As per 12.3.2.4.14 OSPI PHY Module of TRM, OSPI functional clock should be at least 4 times that of OSPI bus clock in order to use No PHY mode. So in order for 143MHz bus clock (as mentioned in data manual), we need an input functional clock of 572MHz. But OSPI module does not support such high functional clock. The Data Manual needs an update and this discussion has rightly triggered that.

Regards,

Karan

Hi,

1.As per 12.3.2.4.14 OSPI PHY Module of TRM,I did not find a description that the functional clock needs to be four times that of the bus clock。What is the function clock here? Is the bus clock OSPI_HCLK?

2.As per 12.3.2.4.1.3 OSPI OSPI Clock Domains Module of TRM,，The data bus clock(OSPI_HCLK) is the main system clock used to transfer data over the data bus between a master on the system interconnect and the OSPI module. The data bus clock also drives the internal OSPI SRAM. The OSPI reference clock (OSPI_RCLK) drives the SPI transmit and receive logic in the OSPI module. It is also used to generate the output SPI protocol clock (OSPI_OCLK) and for oversampling of the input data. Using the reference clock (OSPI_RCLK) allows the OSPI module to decouple the frequency of the SPI flash device from the device system clocks, thereby providing more flexible clocking solution.

At present, my OSPI_HCLK is 333.3MHZ and OSPI_RCLK is 400MHZ. According to your understanding, in order to obtain the maximum flash data transmission speed, should OSPI_RCLK be four times that of OSPI_HCLK?

In reply to Karan Saxena:

Hi,Karan

Do you have a solution to my issue?

1.As per 12.3.2.4.14 OSPI PHY Module of TRM,I did not find a description that the functional clock needs to be four times that of the bus clock。What is the function clock here? What is the bus  clock here?Does it mean OSPI_RCLK and OSPI_HCLK？

2.What is the maximum function clock supported by OSPI module? What is the maximum bus clock? Can the updated value of the datasheet be provided to me？

If you are temporarily unable to give this data, you can tell me the release plan of this data, thank you very much！

Hi,

I think I somehow missed to reply, I had one drafted.

yajuan ma said:

As per 12.3.2.4.14 OSPI PHY Module of TRM,I did not find a description that the functional clock needs to be four times that of the bus clock。What is the function clock here? What is the bus  clock here?Does it mean OSPI_RCLK and OSPI_HCLK？

yajuan ma said:

What is the maximum function clock supported by OSPI module? What is the maximum bus clock? Can the updated value of the datasheet be provided to me？

OSPI0_RCLK is the reference clock for bus clock generation. Internal clocking spec puts it at 400MHz maximum. But maximizing OSPI RCLK alone won't help here. If highest throuhgput is the  OSPI RCLK needs to be set to 166Mhz and PHY + PHY pipeline mode needs to be enabled (in  PHY mode OSPI RCLK = OSPI bus clock and MSTR_BAUD_DIV_FLD is ignored) for max throughput. With 166Mhz Octal DDR mode with PHY + Pipeline mode throughput would be 300MB/s.

As far as the update to the data sheet, I can check that and let you know. I don't have an exact date right now.

Regards,

Karan

Hi,

Karan Saxena said:

As per 12.3.2.4.14 OSPI PHY Module of TRM, OSPI functional clock should be at least 4 times that of OSPI bus clock in order to use No PHY mode. So in order for 143MHz bus clock (as mentioned in data manual), we need an input functional clock of 572MHz. But OSPI module does not support such high functional clock. The Data Manual needs an update and this discussion has rightly triggered that.

A correction here, seems like there is not update required to the Data Manual. So the mistake here was confusing PHY mode with data training. "No data training" still has the PHY on, and the requirement that functional clock be 4x the speed of the bus clock does not apply. But instead of using a tuning algorithm (data training) to select the PHYs TX and RX delays, you use a fixed TX/RX values found in table 5-111. See this note:

So it should be possible to operate at 140MHz if you follow table 5-111.

Apologies for initial confusion.

Regards,

Karan

Hi, Karan,

Thanks for the correction.

Customer engineer has difficulty on realizing high data rate in SDR mode.

Can you help to provide the sample code of achieving the highest data rate in SDR mode?

Thanks. 

Hi ,Karan

Based on your response, I have the following questions:
1. What is data training? How to enable and use data training mode to achieve 5ns (corresponding clock is 200MHz) in 1.8V platform SDR mode?
2. Do you mean that when data training is not used, I can set the most suitable DLL DELAY in PHY mode to achieve a time of 7ns (corresponding clock 142MHz)?
3. Is there any example code to obtain the operation related to the maximum clock frequency?

Thanks!

Hi, Karan,

Customer engineer has tried to use DAC + PHY + PHY pipeline to get maximum OSPI frequency, but failed.

Would you please help to provide the sample code, which is running on J7 EVM with Micron OSPI, to get the highest data rate?

Thanks.

Hi Fan,

Fan_Zhang said:

Customer engineer has tried to use DAC + PHY + PHY pipeline to get maximum OSPI frequency, but failed.

Can you please tell me what is the failure? Also share the code on how are you trying to configure?

I'm looking at some reference code for the same.

Regards,

Karan

Hi, Karan,

Customer engineers feedback that they cannot share the code.

They are sure that DAC, PHY and PHY pipeline are enabled. When setting OSPI_OCLK to 50MHz, it works well. But if setting OSPI_OCLK to 100MHz, the read operation cannot get proper data back.

You can just give them sample code which can be ran on J7 EVM with Micron OSPI that works with highest OSPI_OCLK(e.g. 166MHz), so they can reproduce your result on EVM and porting to customer board.

Thanks.

Hi Fan,

SDK U-Boot does configure OSPI at 166MHz DDR mode for READ  operation U-Boot implementation of training sequence for 166MHz DDR mode is at:

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/drivers/spi/cadence_qspi_apb.c?h=ti-u-boot-2020.01#n474

Dependent code/call stack are at:

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/drivers/spi/cadence_qspi.c?h=ti-u-boot-2020.01

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/drivers/mtd/spi/spi-nor-core.c

HW team is still in the process of publishing appnote for training algo.

Regards,

Karan

Hi, Karan,

Thanks a lot!

Customer engineers are studying the code. Will feedback if any progress or questions.

Thanks.

Hi Fan,

Following is the PDK code for the same, in the unit test.

psdk_rtos_auto_j7_06_02_00_21/pdk/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c line number 781 is the test.

OSPI driver - psdk_rtos_auto_j7_06_02_00_21/pdk/packages/ti/board/src/flash/nor/ospi/nor_ospi.c

Regards,

Karan