Part Number: TDA2EX17EVM
Hi Champs:
Customer is making the TIDL SSD for 720P, he is able to change the EMIF from 512MB to 512X2MB (Dual EMIF) as expected.
Now, he is asking if we are able to enlarge the SR1 ?
and can he modify with DUAL_EMIF with 1GB_512MB?
Please comment, thanks.
BR Rio
hi,
thanks for providing the patch to DUAL_EMIF_2X512MB. i've done for this patch and evm board is now can booting normally on this setup.
1) i'm still wondering why the DUAL_EMIF_2X512MB only enlarge memory size from 330MB to 430MB, not from 330MB to 330MB+512MB( DUAL_EMIF_2X512MB is using more memory from HW, but the software patch is less than HW setup)?
here is the memory map after my modification:
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
L2_ROM 00000000 00004000 000001a0 00003e60 RWIX
L2_RAM 20000000 00010000 00000000 00010000 RWIX
OCMC_RAM1 40300000 00080000 00000000 00080000 RWIX
OCMC_RAM2 40400000 00100000 00000000 00100000 RWIX
OCMC_RAM3 40500000 00100000 00000000 00100000 RWIX
DSP1_L2_SRAM 40800000 00048000 00000000 00048000 RWIX
DSP2_L2_SRAM 41000000 00048000 00000000 00048000 RWIX
NDK_MEM 80000000 00400000 00000000 00400000 RWIX
IPU1_1_CODE_MEM 80400000 00280000 00000000 00280000 RWIX
IPU1_0_CODE_MEM 80680000 00c00000 0053ad08 006c52f8 RWIX
IPU2_CODE_MEM 81280000 00200000 00000000 00200000 RWIX
IPU1_1_DATA_MEM 81480000 00680000 00000000 00680000 RWIX
IPU1_0_DATA_MEM 81b00000 01000000 00915604 006ea9fc RWIX
IPU2_DATA_MEM 82b00000 00700000 00000000 00700000 RWIX
A15_0_DATA_MEM 83900000 00d80000 00000000 00d80000 RWIX
SR1_BUFF_ECC_ASIL_MEM 84680000 00001000 00000000 00001000 RWIX
SR1_BUFF_ECC_QM_MEM 84681000 00001000 00000000 00001000 RWIX
SR1_BUFF_NON_ECC_ASIL 84781000 00001000 00000000 00001000 RWIX
SR1_FRAME_BUFFER_MEM 84782000 1b87d000 00000000 1b87d000 RWIX
SR0 a0000000 00020000 00020000 00000000 RWIX
REMOTE_LOG_MEM a0020000 00028000 000278a0 00000760 RWIX
LINK_STATS_MEM a0048000 00040000 00024df4 0001b20c RWIX
SYSTEM_IPC_SHM_MEM a0088000 00078000 00062388 00015c78 RWIX
SYSTEM_AUTOSAR_IPC_SH a0100000 00080000 00000000 00080000 RWIX
HDVPSS_DESC_MEM a0180000 00100000 0001d4c0 000e2b40 RWIX
EVE1_VECS_MEM a1000000 00080000 00000000 00080000 RWIX
EVE1_CODE_MEM a1080000 00200000 00000000 00200000 RWIX
EVE1_DATA_MEM a1280000 00d80000 00000000 00d80000 RWIX
EVE2_VECS_MEM a2000000 00080000 00000000 00080000 RWIX
EVE2_CODE_MEM a2080000 00200000 00000000 00200000 RWIX
EVE2_DATA_MEM a2280000 00d80000 00000000 00d80000 RWIX
EVE3_VECS_MEM a3000000 00080000 00000000 00080000 RWIX
EVE3_CODE_MEM a3080000 00200000 00000000 00200000 RWIX
EVE3_DATA_MEM a3280000 00d80000 00000000 00d80000 RWIX
EVE4_VECS_MEM a4000000 00080000 00000000 00080000 RWIX
EVE4_CODE_MEM a4080000 00200000 00000000 00200000 RWIX
EVE4_DATA_MEM a4280000 00d80000 00000000 00d80000 RWIX
DSP1_CODE_MEM a5000000 00600000 00000000 00600000 RWIX
DSP2_CODE_MEM a5600000 00400000 00000000 00400000 RWIX
DSP1_DATA_MEM a5a00000 00e00000 00000000 00e00000 RWIX
DSP2_DATA_MEM a6800000 00e00000 00000000 00e00000 RWIX
DSP1_DATA_MEM_2 a7600000 00100000 00000000 00100000 RWIX
DSP2_DATA_MEM_2 a7700000 00100000 00000000 00100000 RWIX
it was actually allocate memory from 0x80000000 to 0xa7800000.(more than 512MB)
2) Even, I change memory map successfully, the modification for DUAL_EMIF_2X512MB still makes me confused. So, a few question as below:
1. On mem_segment_definition_bios.xs, why virtual address setup disabled for DUAL_EMIF_2X512MB setting? why is it necessary for SINGLE_EMIF_512MB?
2. On a15_0.cfg, why do we need to changing Mmu.setSecondLevelDescMeta(i, i-0x20000000, attrs2); to Mmu.setSecondLevelDescMeta(i, i, attrs2);? why it need to be offset 0x20000000 for SINGLE_EMIF_512MB?
3. On Ammu1_bios.cfg & Ammu2_bios.cfg, why we need to enable the fourth AMMU block for DUAL_EMIF_2X512MB, and disable it for SINGLE_EMIF_512MB? (As my understanding, it should be only two sections for DUAL_EMIF_2X512MB, and each of them allocate 512MB. (please correct me if i wrong) )
4. On system_bsp_init.c, why we need to disable virtual memory mapping function for DUAL_EMIF_2X512MB?
3) However, I was trying to setup SINGLE_EMIF_1GB. At first, I referred to TRM and I modified the HW setup inside SBL(as following figure),
and then I modified the memory map to SINGLE_EMIF_1GB.
But, the evm board stuck on booting (message as shown below).
TDA2xx SBL Boot
DPLL Configuration Completed
Clock Domain Configuration Completed
Module Enable Configuration Completed
TI EVM PAD Config Completed
>> START ==> Overall DDR configuration
>> START ==> EMIF1 and EMIF1 DDR IOs config (CTRL_MODULE_CORE_PAD module)
Launch full leveling
Updating slave ratios in PHY_STATUSx registers
as per HW leveling output
HW leveling is now disabled. Using slave ratios from
PHY_STATUSx registers
One EMIF - 1GB total memory
Same memory mapped at 0x80000000 and 0xC0000000
>> END ==> overall DDR configuration completed / DDR memory can now be accessed
DDR Config Completed
App Image Download Begins
SD Boot - file open completed successfully
MPU CPU0 Image Load Completed
IPU1 CPU0 Image Load Completed
IPU1 CPU1 Image Load Completed
IPU2 CPU0 and CPU1 Image Load Completed
DSP1 Image Load Completed
DSP2 Image Load Completed
EVE1 Image Load Completed
EVE2 Image Load Completed
EVE3 Image Load Completed
EVE4 Image Load Completed
App Image Download Completed
Putting MPU CPU1 in Off mode
EVE MMU configuration completed
EVE MMU configuration completed
EVE MMU configuration completed
EVE MMU configuration completed
*****************************************************************
PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles
SBL Initial Config Cycles - 144642 (12.34 ms)
SOC Init Cycles - 264207 (22.54 ms)
DDR Config Clock Cycles - 884131 (75.44 ms)
App Image Load Cycles - 43980466 (3752.99 ms)
Slave Core Bootup Cycles - 322632 (27.53 ms)
SBL Boot-up Cycles - 45597413 (3890.97 ms)
Time at which SBL started IPU1_0 - 90375 (2758.2 ms)
*****************************************************************
Jumping to MPU CPU0 App
Thanks
Best regards,
Wxchen