66AK2H06: USB Clock AC coupling requirement

Tashiro-san,

What previous discussion are you referencing?  Why do you think that you need to add a 100-ohm termination?

The 66AK2H device contains multiple reference clock input types.  The main PLL inputs have LJCB input buffers.  The SERDES blocks have input buffers unique to those SERDES blocks.  Similarly, the USB block has a unique buffer for its logic.  Not all KeyStone-II devices have the same type of USB input clock buffer so that is why the requirement for AC-coupling is footnoted.  I see that the EVM uses a DC-coupled circuit.  What is the signaling type of the USB clock source?  You might need to use DC-coupling assuming the single-ended DC levels are compatible this the USBCLK input buffer.

Tom

Hi Tom,

I meant the previous discussion is below;
https://e2e.ti.com/support/processors/f/791/t/900484

Here is your comments:
I did some more research. I found that the USB IP block is different that the other SERDES IP blocks on this device. As you can see, it is not mentioned in the KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide (SPRUHO3A). The SERDES reference clocks are the ones that require the software driver to be executed before the reference clock is properly terminated. The USB-SS interface is described in the KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide (SPRUHJ7A).  However, I cannot find any reference to software control for the termination for the reference clock input.  I do know that the USB-SS port on the 66AK2H14 device has passed our compliance tests.  I expect that we passed our tests with the same clock that the customer is seeing.  Since it passes compliance without the external termination resistor and since the reference clock signal still meets the LVDS signal definition when the external resistor is added, the customer can choose to either add the external termination or leave it off.

The driver side datasheet is below:
https://www.idt.com/jp/ja/document/dst/idt8slvd1208-33i-datasheet

Thanks and regards,
Koichiro Tashiro

Tashiro-san,

We will need to see the single-ended output signal from the driver.  3.3V LVDS can potentially drive a voltage that is above the maximum input level.  You also see that AC-coupling is challenging the absolute minimum level.  The best solution is probably continuing to use AC-coupling and to add a DC-bias on one of the clock input pins as shown in the Clocking Design Guide for KeyStone Devices Application Report (SPRABI4) in Figure 21.  Connecting a voltage divider as shown between the 0.85V supply voltage into the VP pin and ground will provide a DC bias such that the single-ended clock signals remain away from the absolute limits.  Note that there are other solutions to this issue but this is the simplest.

Tom

Hi Tom,

I thought the driver is LVDS and the receiver is SerDes/CML.
If my understanding is correct, Figure 28 (SPRABI4) should be the right reference?
And Vt2(3.3V) in below figure will be 0.85V and it adds ~0.425V DC offset in our case?


The figure applies DC-bias(pull-up/down) on only one side.
Is this enough? We do not need both?

Thanks and regards,
Koichiro Tashiro

Hi Tom,

Thanks for your explanation. Now customer understand following.
Is this correct implementation you suggested?



Could you explain a bit more about below comment? Is there any guideline to select the resistor values?

>The resistors in the divider could be larger values - even in excess of 100K ohms.

Thanks and regards,
Koichiro Tashiro

Tashiro-san,

Use of the voltage divider using 10K resistors is acceptable.  However, some designers want to minimize the current consumed.  Therefore, higher value resistors can be used to reduce this current consumption.  This is also acceptable since the input impedance to ground is very high (>1MOhm).

Tom

Hi Tom,

Thanks for clarifying the resistor value.
Other parts in the customer diagram are OK?

In that diagram, PU/PD are on USBCLKM signal, but it does not matter either UBSCLKM or USBCLKP, right?

Thanks and regards,
Koichiro Tashiro

Hi Tom,

Thanks!
Customer tried below modification on their board and confirmed both USBCLKP and USBCLKM are properly offset ~0.425V.

It is difficult to get to this configuration reading from current Hardware Design Guide(sprabv0.pdf), section 3 Clocking.
Could you update the description?

Thanks and regards,
Koichiro Tashiro